DVR datasheet(201/416 Pages) MICROCHIP

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DS30010118D-page 201

PIC24FJ256GA705 FAMILY

17.0 SERIAL PERIPHERAL

INTERFACE (SPI)

The Serial Peripheral Interface (SPI) module is a

synchronous serial interface useful for communicating

with other peripheral or microcontroller devices. These

peripheral devices may be serial EEPROMs, shift

registers, display drivers, A/D Converters, etc. The SPI

module is compatible with the Motorola® SPI and SIOP

interfaces. All devices in the PIC24FJ256GA705 family

include three SPI modules.

The module supports operation in two buffer modes. In

Standard Buffer mode, data is shifted through a single

serial buffer. In Enhanced Buffer mode, data is shifted

through a FIFO buffer. The FIFO level depends on the

configured mode.

Variable length data can be transmitted and received

from 2 to 32 bits.

The module also supports a basic framed SPI protocol

while operating in either Master or Slave mode. A total

of four framed SPI configurations are supported.

The module also supports Audio modes. Four different

Audio modes are available.

•I2S mode

• Left Justified mode

• Right Justified mode

• PCM/DSP mode

In each of these modes, the serial clock is free-running

and audio data is always transferred.

If an audio protocol data transfer takes place between

two devices, then usually one device is the master and

the other is the slave. However, audio data can be

transferred between two slaves. Because the audio

protocols require free-running clocks, the master can

be a third party controller. In either case, the master

generates two free-running clocks: SCKx and LRC

(Left, Right Channel Clock/SSx/FSYNC).

The SPI serial interface consists of four pins:

• SDIx: Serial Data Input

• SDOx: Serial Data Output

• SCKx: Shift Clock Input or Output

• SSx: Active-Low Slave Select or Frame

Synchronization I/O Pulse

The SPI module can be configured to operate using

two, three or four pins. In 3-pin mode, SSx is not used.

In 2-pin mode, both SDOx and SSx are not used.

The SPI module has the ability to generate three inter-

rupts reflecting the events that occur during the data

communication. The following types of interrupts can

be generated:

Receive interrupts are signalled by SPIxRXIF.

This event occurs when:

- RX watermark interrupt

- SPIROV = 1

- SPIRBF = 1

- SPIRBE = 1

provided the respective mask bits are enabled in

SPIxIMSKL/H.

Transmit interrupts are signalled by SPIxTXIF.

This event occurs when:

- TX watermark interrupt

- SPITUR = 1

- SPITBF = 1

- SPITBE = 1

provided the respective mask bits are enabled in

SPIxIMSKL/H.

General interrupts are signalled by SPIxIF. This

event occurs when

- FRMERR = 1

- SPIBUSY = 1

-SRMT = 1

provided the respective mask bits are enabled in

SPIxIMSKL/H.

A block diagram of the module in Enhanced Buffer mode

is shown in Figure 17-1.

Note:

This data sheet summarizes the features of

the PIC24FJ256GA705 family of devices. It

is not intended to be a comprehensive

reference source. To complement the

information in this data sheet, refer to the

“dsPIC33/PIC24

Family

Reference

Manual”, “Serial Peripheral Interface

(SPI) with Audio Codec Support”

(DS70005136), which is available from the

Microchip website (www.microchip.com).

The

information

in this

data

sheet

supersedes the information in the FRM.

Note:

Do not perform Read-Modify-Write opera-

tions (such as bit-oriented instructions) on

the SPIxBUF register in either Standard or

Enhanced Buffer mode.

Note:

In this section, the SPI modules are

referred to together as SPIx, or separately

as SPI1, SPI2 or SPI3. Special Function

Registers will follow a similar notation. For

example, SPIxCON1 and SPIxCON2

refer to the control registers for any of the

three SPI modules.

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