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DVR 数据表(PDF) 204 Page - Microchip Technology |
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DVR 数据表(HTML) 204 Page - Microchip Technology |
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204 / 416 page  PIC24FJ256GA705 FAMILY DS30010118D-page 204 2016-2018 Microchip Technology Inc. 17.4 SPI Control Registers REGISTER 17-1: SPIxCON1L: SPIx CONTROL REGISTER 1 LOW R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SPIEN — SPISIDL DISSDO MODE32(1,4) MODE16(1,4) SMP CKE(1) bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SSEN(2) CKP MSTEN DISSDI DISSCK MCLKEN(3) SPIFE ENHBUF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 SPIEN: SPIx On bit 1 = Enables module 0 = Turns off and resets module, disables clocks, disables interrupt event generation, allows SFR modifications bit 14 Unimplemented: Read as ‘0’ bit 13 SPISIDL: SPIx Stop in Idle Mode bit 1 = Halts in CPU Idle mode 0 = Continues to operate in CPU Idle mode bit 12 DISSDO: Disable SDOx Output Port bit 1 = SDOx pin is not used by the module; pin is controlled by the port function 0 = SDOx pin is controlled by the module bit 11-10 MODE<32,16>: Serial Word Length bits(1,4) AUDEN = 0: MODE32 MODE16 COMMUNICATION FIFO DEPTH 1x 32-Bit 8 01 16-Bit 16 00 8-Bit 32 AUDEN = 1: MODE32 MODE16 COMMUNICATION 11 24-Bit Data, 32-Bit FIFO, 32-Bit Channel/64-Bit Frame 10 32-Bit Data, 32-Bit FIFO, 32-Bit Channel/64-Bit Frame 01 16-Bit Data, 16-Bit FIFO, 32-Bit Channel/64-Bit Frame 00 16-Bit Data, 16-Bit FIFO, 16-Bit Channel/32-Bit Frame bit 9 SMP: SPIx Data Input Sample Phase bit Master Mode: 1 = Input data is sampled at the end of data output time 0 = Input data is sampled at the middle of data output time Slave Mode: Input data is always sampled at the middle of data output time, regardless of the SMP setting. Note 1: When AUDEN = 1, this module functions as if CKE = 0, regardless of its actual value. 2: When FRMEN = 1, SSEN is not used. 3: MCLKEN can only be written when the SPIEN bit = 0. 4: This channel is not meaningful for DSP/PCM mode as LRC follows the FRMSYPW bit. 5: The MCLK source is the REFO clock. |
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