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DVR 数据表(PDF) 330 Page - Microchip Technology |
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DVR 数据表(HTML) 330 Page - Microchip Technology |
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330 / 416 page  PIC24FJ256GA705 FAMILY DS30010118D-page 330 2016-2018 Microchip Technology Inc. REGISTER 29-1: FSEC CONFIGURATION REGISTER U-1 U-1 U-1 U-1 U-1 U-1 U-1 U-1 — — — — — — — — bit 23 bit 16 R/PO-1 U-1 U-1 U-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 AIVTDIS — — — CSS2 CSS1 CSS0 CWRP bit 15 bit 8 R/PO-1 R/PO-1 R/PO-1 U-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 GSS1 GSS0 GWRP — BSEN BSS1 BSS0 BWRP bit 7 bit 0 Legend: PO = Program Once bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 23-16 Unimplemented: Read as ‘1’ bit 15 AIVTDIS: Alternate Interrupt Vector Table Disable bit 1 = Disables AIVT; INTCON2<8> (AIVTEN) bit is not available 0 = Enables AIVT; INTCON2<8> (AIVTEN) bit is available bit 14-12 Unimplemented: Read as ‘1’ bit 11-9 CSS<2:0>: Configuration Segment (CS) Code Protection Level bits 111 = No protection (other than CWRP) 110 = Standard security 10x = Enhanced security 0xx = High security bit 8 CWRP: Configuration Segment Program Write Protection bit 1 = Configuration Segment is not write-protected 0 = Configuration Segment is write-protected bit 7-6 GSS<1:0>: General Segment (GS) Code Protection Level bits 11 = No protection (other than GWRP) 10 = Standard security 0x = High security bit 5 GWRP: General Segment Program Write Protection bit 1 = General Segment is not write-protected 0 = General Segment is write-protected bit 4 Unimplemented: Read as ‘1’ bit 3 BSEN: Boot Segment (BS) Control bit 1 = No Boot Segment is enabled 0 = Boot Segment size is determined by BSLIM<12:0> bit 2-1 BSS<1:0>: Boot Segment Code Protection Level bits 11 = No protection (other than BWRP) 10 = Standard security 0x = High security bit 0 BWRP: Boot Segment Program Write Protection bit 1 = Boot Segment can be written 0 = Boot Segment is write-protected |
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