STM32L082KB datasheet(20/132 Pages) STMICROELECTRONICS

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Functional overview

STM32L082xx

20/132

DS10688 Rev 7

3.3

Arm® Cortex®-M0+ core with MPU

The Cortex-M0+ processor is an entry-level 32-bit Arm Cortex processor designed for a

broad range of embedded applications. It offers significant benefits to developers, including:

•

a simple architecture that is easy to learn and program

•

ultra-low power, energy-efficient operation

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excellent code density

•

deterministic, high-performance interrupt handling

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upward compatibility with Cortex-M processor family

•

platform security robustness, with integrated Memory Protection Unit (MPU).

The Cortex-M0+ processor is built on a highly area and power optimized 32-bit processor

core, with a 2-stage pipeline Von Neumann architecture. The processor delivers exceptional

energy efficiency through a small but powerful instruction set and extensively optimized

design, providing high-end processing hardware including a single-cycle multiplier.

The Cortex-M0+ processor provides the exceptional performance expected of a modern 32-

bit architecture, with a higher code density than other 8-bit and 16-bit microcontrollers.

Owing to its embedded Arm core, the STM32L082xx are compatible with all Arm tools and

software.

Nested vectored interrupt controller (NVIC)

The ultra-low-power STM32L082xx embed a nested vectored interrupt controller able to

handle up to 32 maskable interrupt channels and 4 priority levels.

The Cortex-M0+ processor closely integrates a configurable Nested Vectored Interrupt

Controller (NVIC), to deliver industry-leading interrupt performance. The NVIC:

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includes a Non-Maskable Interrupt (NMI)

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provides zero jitter interrupt option

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provides four interrupt priority levels

The tight integration of the processor core and NVIC provides fast execution of Interrupt

Service Routines (ISRs), dramatically reducing the interrupt latency. This is achieved

through the hardware stacking of registers, and the ability to abandon and restart load-

multiple and store-multiple operations. Interrupt handlers do not require any assembler

wrapper code, removing any code overhead from the ISRs. Tail-chaining optimization also

significantly reduces the overhead when switching from one ISR to another.

To optimize low-power designs, the NVIC integrates with the sleep modes, that include a

deep sleep function that enables the entire device to enter rapidly stop or standby mode.

This hardware block provides flexible interrupt management features with minimal interrupt

latency.

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