STM32H757AI datasheet(49/251 Pages) STMICROELECTRONICS

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DS12931 Rev 1

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STM32H757xI

Functional overview

The LPUART has a clock domain independent from the CPU clock, and can wakeup the

system from Stop mode. The wakeup from Stop mode are programmable and can be done

on:

•

Start bit detection

•

Any received data frame

•

A specific programmed data frame

•

Specific TXFIFO/RXFIFO status when FIFO mode is enabled.

Only a 32.768 kHz clock (LSE) is needed to allow LPUART communication up to

9600 baud. Therefore, even in Stop mode, the LPUART can wait for an incoming frame

while having an extremely low energy consumption. Higher speed clock can be used to

reach higher baudrates.

LPUART interface can be served by the DMA controller.

3.35

Serial peripheral interface (SPI)/inter- integrated sound

interfaces (I2S)

The devices feature up to six SPIs (SPI2S1, SPI2S2, SPI2S3, SPI4, SPI5 and SPI6) that

allow communicating up to 150 Mbits/s in Master and Slave modes, in Half-duplex, Full-

duplex and Simplex modes. The 3-bit prescaler gives 8 master mode frequencies and the

frame is configurable from 4 to 16 bits. All SPI interfaces support NSS pulse mode, TI mode,

Hardware CRC calculation and 8x 8-bit embedded Rx and Tx FIFOs with DMA capability.

Three standard I2S interfaces (multiplexed with SPI1, SPI2 and SPI3) are available. They

can be operated in Master or Slave mode, in Simplex communication modes, and can be

configured to operate with a 16-/32-bit resolution as an input or output channel. Audio

sampling frequencies from 8 kHz up to 192 kHz are supported. When either or both of the

I2S interfaces is/are configured in Master mode, the master clock can be output to the

external DAC/CODEC at 256 times the sampling frequency. All I2S interfaces support 16x 8-

bit embedded Rx and Tx FIFOs with DMA capability.

3.36

Serial audio interfaces (SAI)

The devices embed 4 SAIs (SAI1, SAI2, SAI3 and SAI4) that allow designing many stereo

or mono audio protocols such as I2S, LSB or MSB-justified, PCM/DSP, TDM or AC’97. An

SPDIF output is available when the audio block is configured as a transmitter. To bring this

level of flexibility and reconfigurability, the SAI contains two independent audio sub-blocks.

Each block has it own clock generator and I/O line controller.

Audio sampling frequencies up to 192 kHz are supported.

In addition, up to 8 microphones can be supported thanks to an embedded PDM interface.

The SAI can work in master or slave configuration. The audio sub-blocks can be either

receiver or transmitter and can work synchronously or asynchronously (with respect to the

other one). The SAI can be connected with other SAIs to work synchronously.

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