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数据搜索系统，热门电子元器件搜索 |
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STM32H757AI 数据表(PDF) 18 Page - STMicroelectronics |
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STM32H757AI 数据表(HTML) 18 Page - STMicroelectronics |
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18 / 251 page  Description STM32H757xI 18/251 DS12931 Rev 1 Figure 1. STM32H757xI block diagram MSv43738V13 FDCAN1 FDCAN2 I2C1/SMBUS I2C2/SMBUS I2C3/SMBUS AXI/AHB12 (200MHz) 4 compl. chan. (TIM1_CH1[1:4]N), 4 chan. (TIM1_CH1[1:4]ETR, BKIN as AF TX, RX SCL, SDA, SMBAL as AF MDMA PK[7:0] 4 compl. chan.(TIM8_CH1[1:4]N), 4 chan. (TIM8_CH1[1:4], ETR, BKIN as AF RX, TX, SCK, CTS, RTS as AF SCL, SDA, SMBAL as AF SCL, SDA, SMBAL as AF MOSI, MISO, SCK, NSS/SDO, SDI, CK, WS, MCK, as AF TX, RX RX, TX as AF RX, TX as AF RX, TX, SCK CTS, RTS as AF RX, TX, SCK, CTS, RTS as AF 1 channel as AF smcard irDA 1 channel as AF 2 channels as AF 4 channels 4 channels, ETR as AF 4 channels, ETR as AF 4 channels, ETR as AF RX, TX as AF FIFO LCD-TFT FIFO CHROM-ART (DMA2D) SD, SCK, FS, MCLK as AF LCD_R[7:0], LCD_G[7:0], LCD_B[7:0], LCD_HSYNC, LCD_VSYNC, LCD_DE, LCD_CLK CLK, CS,D[7:0] CEC as AF IN[1:4] as AF MDC, MDIO AXIM AXIM AHBP AHBS TRACECK TRACED[3:0] JTRST, JTDI, JTCK/SWCLK JTDO/SWD, JTDO JTAG/SW ETM I-Cache 16KB D-Cache 16KB I- TCM 4KB D- TCM 64KB 16 Streams FIFO SDMMC1 SDMMC_D[7:0],SDMMC_D[7:3,1]Dir SDMMC_D0dir, SDMMC_D2dir CMD, CMDdir, CK, Ckin, CKio as AF FIFO DMA1 FIFOs 8 Stream DMA2 FIFOs ETHER MAC SDMMC2 FIFO OTG_HS FIFO OTG_FS FIFO SRAM1 128 KB 8 Stream FMC_signals DMA DMA/ DMA/ PHY PHY MII / RMII MDIO as AF DP, DM, STP, NXT,ULPI:CK , D[7:0], DIR, ID, VBUS ADC1 DAC1_OUT, DAC2_OUT as AF 16b AXI/AHB34 (200MHz) JPEG WWDG1 AHB2 (200MHz) PA..J[15:0] HSYNC, VSYNC, PUIXCLK, D[13:0] SAI3 MOSI, MISO, SCK, NSS as AF MOSI, MISO, SCK, NSS as AF smcard irDA 32-bit AHB BUS-MATRIX 32-bit AHB BUS-MATRIX BDMA DMA Mux2 Up to 20 analog inputs common to ADC1 & 2 HSEM AHB4 VDDA, VSSA NRESET WKUP[5:0] @VDD RCC Reset & control OSC32_IN OSC32_OUT VBAT = 1.2 to 3.6 V AWU VDD12 OSC_IN OSC_OUT RTC_TS RTC_TAMP[1:3] RTC_OUT RTC_REFIN VDD = 1.62 to 3.6V VDDUSB33 = 3.0 to 3.6V VDDDSI = 1.8 to 3.6V VSS VCAP VDDMMC33 = 1.8 to 3.6 V VDDSMPS, VSSSMPS VLXSMPS, VFBSMPS @VDD @VDD33 @VSW SUPPLY SUPERVISION Int POR reset @VDD LPTIM1_IN1, LPTIM1_IN2, LPTIM1_OUT as AF OPAMPx_VINM OPAMPx_VINP OPAMPx_VOUT as AF HRTIM1_CH[A..E]x HRTIM1_FLT[5:1], HRTIM1_FLT[5:1]_in, SYSFLT DFSDM1_CKOUT, DFSDM1_DATAIN[0:7], DFSDM1_CKIN[0:7] 2 compl. chan.(TIM15_CH1[1:2]N), 2 chan. (TIM_CH15[1:2], BKIN as AF 1 compl. chan.(TIM16_CH1N), 1 chan. (TIM16_CH1, BKIN as AF 1 compl. chan.(TIM17_CH1N), 1 chan. (TIM17_CH1, BKIN as AF SDMMC_ D[7:0], CMD, CK as AF Up to 17 analog inputs common to ADC1 and 2 SD, SCK, FS, MCLK, PDM_DI/CK[4:1] as AF SCL, SDA, SMBAL as AF COMPx_INP, COMPx_INM, COMPx_OUT as AF LPTIM5_OUT as AF D- TCM 64KB AHB/APB Quad-SPI 1 MB FLASH 1 MB FLASH 512 KB AXI SRAM FMC Delay block DCMI AHB/APB HRTIM1 DFSDM1 SD, SCK, FS, MCLK as AF SAI2 SD, SCK, FS, MCLK, D[3:1], CK[2:1] as AF SAI1 SPI5 TIM17 TIM16 TIM15 SPI4 MOSI, MISO, SCK, NSS/ SDO, SDI, CK, WS, MCK, as AF SPI/I2S1 USART6 RX, TX, SCK, CTS, RTS as AF irDA USART1 TIM1/PWM 16b TIM8/PWM 16b ADC3 GPIO PORTA.. J GPIO PORTK SAI4 COMP1&2 LPTIM5 LPTIM4_OUT as AF LPTIM4 LPTIM3_OUT as AF LPTIM3 I2C4 MISO, MOSI, SCK, NSS as AF SPI6 RX, TX, CK, CTS, RTS as AF LPUART1 LPTIM2 VREF SYSCFG EXTI WKUP CRC DAP DMA Mux1 To APB1-2 peripherals SRAM2 128 KB SRAM3 32 KB ADC2 AHB/APB TIM6 16b TIM7 16b SWPMI TIM2 32b TIM3 16b TIM4 16b TIM5 32b TIM12 16b TIM13 16b TIM14 16b USART2 smcard irDA USART3 UART4 UART5 UART7 RX, TX as AF UART8 SPI2/I2S2 MOSI, MISO, SCK, NSS/SDO, SDI, CK, WS, MCK, as AF SPI3/I2S3 MDIOS RAM I/F CRS SPDIFRX1 HDMI-CEC DAC1&2 LPTIM1 OPAMP1&2 AHB/APB XTAL 32 kHz RTC Backup registers XTAL OSC 4- 48 MHz 32 KHz LSI RC PLL1+PLL2+PLL3 POR/PDR/BOR PVD smcard LSI HSI CSI RC48 LPTIM2_OUT as AF AHB1 (200MHz) DP, DM, ID, VBUS 64 KB SRAM 4 KB BKP RAM ARM Cortex M4 Arm Cortex M7 I- Bus D- Bus S- Bus D S I DSI_D0_P, DSI_D0_N DSI_D1_P, DSI_D1_N DSI_CK_P, DSI_CK_N ART (instruction cache) AHB ART (200MHz) RNG WWDG2 IWDG1 IWDG2 Voltage regulator 3.3 to 1.2V SMPS step-down converter 4 MHz CSI 48 MHz HSI48 RC 64 MHz HSI RC IWDG1 IWDG2 HASH 3DES/AES VDDREF_ADC Tem. sensor |
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