STM32H757AI datasheet(23/251 Pages) STMICROELECTRONICS

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DS12931 Rev 1

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STM32H757xI

Functional overview

3.3.3

Embedded SRAM

All devices feature around 1 Mbyte of RAM with hardware ECC. The RAM is divided as

follows:

•

512 Kbytes of AXI-SRAM mapped onto AXI bus on D1 domain.

•

SRAM1 mapped on D2 domain: 128 Kbytes

•

SRAM2 mapped on D2 domain: 128 Kbytes

•

SRAM3 mapped on D2 domain: 32 Kbytes

•

SRAM4 mapped on D3 domain: 64 Kbytes

•

4 Kbytes of backup SRAM

The content of this area is protected against possible unwanted write accesses,

and is retained in Standby or VBAT mode.

•

RAM mapped to TCM interface (ITCM and DTCM):

Both ITCM and DTCM RAMs are 0 wait state memories. They can be accessed either

from the Arm® Cortex®-M7 CPU or the MDMA (even in Sleep mode) through a specific

AHB slave of the Cortex®-M7(AHBS):

–

64 Kbytes of ITCM-RAM (instruction RAM)

This RAM is connected to ITCM 64-bit interface designed for execution of critical

real-times routines by the Cortex®-M7.

–

128 Kbytes of DTCM-RAM (2x 64-Kbyte DTCM-RAMs on 2x32-bit DTCM ports)

The DTCM-RAM could be used for critical real-time data, such as interrupt service

routines or stack/heap memory. Both DTCM-RAMs can be used in parallel (for

load/store operations) thanks to the Cortex®-M7 dual issue capability.

The MDMA can be used to load code or data in ITCM or DTCM RAMs.

Error code correction (ECC)

Over the product lifetime, and/or due to external events such as radiations, invalid bits in

memories may occur. They can be detected and corrected by ECC. This is an expected

behavior that has to be managed at final-application software level in order to ensure data

integrity through ECC algorithms implementation.

SRAM data are protected by ECC:

•

7 ECC bits are added per 32-bit word.

•

8 ECC bits are added per 64-bit word for AXI-SRAM and ITCM-RAM.

The ECC mechanism is based on the SECDED algorithm. It supports single-error correction

and double-error detection.

3.3.4

ART™ accelerator

The ART™ (adaptive real-time) accelerator block speeds up instruction fetch accesses of

the Cortex®-M4 core from D1-domain internal memories (Flash memory bank 1, Flash

memory bank 2, AXI SRAM) and from D1-domain external memories attached via Quad-

SPI controller and Flexible memory controller (FMC).

The ART™ accelerator is a 256-bit cache line using 64-bit WRAP4 accesses from the 64-bit

AXI D1 domain. The acceleration is achieved by loading selected code into an embedded

cache and making it instantly available to Cortex®-M4 core, thus avoiding latency due to

memory wait states.

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