STM32H757AI datasheet(53/251 Pages) STMICROELECTRONICS

53 / 251 page

DS12931 Rev 1

53/251

STM32H757xI

Functional overview

The devices include the following features:

•

Supports 10 and 100 Mbit/s rates

•

Dedicated DMA controller allowing high-speed transfers between the dedicated SRAM

and the descriptors

•

Tagged MAC frame support (VLAN support)

•

Half-duplex (CSMA/CD) and full-duplex operation

•

MAC control sublayer (control frames) support

•

32-bit CRC generation and removal

•

Several address filtering modes for physical and multicast address (multicast and

group addresses)

•

32-bit status code for each transmitted or received frame

•

Internal FIFOs to buffer transmit and receive frames. The transmit FIFO and the

receive FIFO are both 2 Kbytes.

•

Supports hardware PTP (precision time protocol) in accordance with IEEE 1588 2008

(PTP V2) with the time stamp comparator connected to the TIM2 input

•

Triggers interrupt when system time becomes greater than target time

3.44

High-definition multimedia interface (HDMI)

- consumer electronics control (CEC)

The devices embed a HDMI-CEC controller that provides hardware support for the

Consumer Electronics Control (CEC) protocol (Supplement 1 to the HDMI standard).

This protocol provides high-level control functions between all audiovisual products in an

environment. It is specified to operate at low speeds with minimum processing and memory

overhead. It has a clock domain independent from the CPU clock, allowing the HDMI-CEC

controller to wakeup the MCU from Stop mode on data reception.

3.45

Debug infrastructure

The devices offer a comprehensive set of debug and trace features on both cores to support

software development and system integration.

•

Breakpoint debugging

•

Code execution tracing

•

Software instrumentation

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JTAG debug port

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Serial-wire debug port

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Trigger input and output

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Serial-wire trace port

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Trace port

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Arm® CoreSight™ debug and trace components

The debug can be controlled via a JTAG/Serial-wire debug access port, using industry

standard debugging tools. The debug infrastructure allows debugging one core at a time, or

both cores in parallel.

The trace port performs data capture for logging and analysis.

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