STM32H757AI datasheet(41/251 Pages) STMICROELECTRONICS

41 / 251 page

DS12931 Rev 1

41/251

STM32H757xI

Functional overview

The JPEG codec main features are as follows:

•

8-bit/channel pixel depths

•

Single clock per pixel encoding and decoding

•

Support for JPEG header generation and parsing

•

Up to four programmable quantization tables

•

Fully programmable Huffman tables (two AC and two DC)

•

Fully programmable minimum coded unit (MCU)

•

Encode/decode support (non simultaneous)

•

Single clock Huffman coding and decoding

•

Two-channel interface: Pixel/Compress In, Pixel/Compressed Out

•

Support for single greyscale component

•

Ability to enable/disable header processing

•

Fully synchronous design

•

Configuration for High-speed decode mode

3.28

Random number generator (RNG)

All devices embed an RNG that delivers 32-bit random numbers generated by an integrated

analog circuit.

3.29

Cryptographic acceleration (CRYP and HASH)

The devices embed a cryptographic processor that supports the advanced cryptographic

algorithms usually required to ensure confidentiality, authentication, data integrity and non-

repudiation when exchanging messages with a peer:

•

Encryption/Decryption

–

DES/TDES (data encryption standard/triple data encryption standard): ECB

(electronic codebook) and CBC (cipher block chaining) chaining algorithms, 64-,

128- or 192-bit key

–

AES (advanced encryption standard): ECB, CBC, GCM, CCM, and CTR (Counter

mode) chaining algorithms, 128, 192 or 256-bit key

•

Universal HASH

–

SHA-1 and SHA-2 (secure HASH algorithms)

–MD5

–HMAC

The cryptographic accelerator supports DMA request generation.

3.30

Timers and watchdogs

The devices include one high-resolution timer, two advanced-control timers, ten general-

purpose timers, two basic timers, five low-power timers, two watchdogs and a SysTick timer.

All timer counters can be frozen in Debug mode.

Table 5 compares the features of the advanced-control, general-purpose and basic timers.

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