STM32H757AI datasheet(32/251 Pages) STMICROELECTRONICS

32 / 251 page

Functional overview

STM32H757xI

32/251

DS12931 Rev 1

3.10

DMA controllers

The devices feature four DMA instances to unload CPU activity:

•

A master direct memory access (MDMA)

The MDMA is a high-speed DMA controller, which is in charge of all types of memory

transfers (peripheral to memory, memory to memory, memory to peripheral), without

any CPU action. It features a master AXI interface and a dedicated AHB interface to

access Cortex®-M7 TCM memories.

The MDMA is located in D1 domain. It is able to interface with the other DMA

controllers located in D2 domain to extend the standard DMA capabilities, or can

manage peripheral DMA requests directly.

Each of the 16 channels can perform single block transfers, repeated block transfers

and linked list transfers.

•

Two dual-port DMAs (DMA1, DMA2) located in D2 domain, with FIFO and request

router capabilities.

•

One basic DMA (BDMA) located in D3 domain, with request router capabilities.

The DMA request router could be considered as an extension of the DMA controller. It

routes the DMA peripheral requests to the DMA controller itself. This allowing managing the

DMA requests with a high flexibility, maximizing the number of DMA requests that run

concurrently, as well as generating DMA requests from peripheral output trigger or DMA

event.

3.11

Chrom-ART Accelerator™ (DMA2D)

The Chrom-Art Accelerator™ (DMA2D) is a graphical accelerator which offers advanced bit

blitting, row data copy and pixel format conversion. It supports the following functions:

•

Rectangle filling with a fixed color

•

Rectangle copy

•

Rectangle copy with pixel format conversion

•

Rectangle composition with blending and pixel format conversion

Various image format coding are supported, from indirect 4bpp color mode up to 32bpp

direct color. It embeds dedicated memory to store color lookup tables. The DMA2D also

supports block based YCbCr to handle JPEG decoder output.

An interrupt can be generated when an operation is complete or at a programmed

watermark.

All the operations are fully automatized and are running independently from the CPU or the

DMAs.

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