STM32H757AI datasheet(30/251 Pages) STMICROELECTRONICS

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Functional overview

STM32H757xI

30/251

DS12931 Rev 1

The RCC provides three PLLs: one for system clock, two for kernel clocks.

The system starts on the HSI clock. The user application can then select the clock

configuration.

3.7.2

System reset sources

Power-on reset initializes all registers while system reset reinitializes the system except for

the debug, part of the RCC and power controller status registers, as well as the backup

power domain.

A system reset is generated in the following cases:

•

Power-on reset (pwr_por_rst)

•

Brownout reset

•

Low level on NRST pin (external reset)

•

Independent watchdog 1 (from D1 domain)

•

Independent watchdog 2 (from D2 domain)

•

Window watchdog 1 (from D1 domain)

•

Window watchdog 2 (from D2 domain)

•

Software reset

•

Low-power mode security reset

•

Exit from Standby

3.8

General-purpose input/outputs (GPIOs)

Each of the GPIO pins can be configured by software as output (push-pull or open-drain,

with or without pull-up or pull-down), as input (floating, with or without pull-up or pull-down)

or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog

alternate functions. All GPIOs are high-current-capable and have speed selection to better

manage internal noise, power consumption and electromagnetic emission.

After reset, all GPIOs (except debug pins) are in Analog mode to reduce power

consumption (refer to GPIOs register reset values in the device reference manual).

The I/O configuration can be locked if needed by following a specific sequence in order to

avoid spurious writing to the I/Os registers.

3.9

Bus-interconnect matrix

The devices feature an AXI bus matrix, two AHB bus matrices and bus bridges that allow

interconnecting bus masters with bus slaves (see Figure 5).

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