STM32H757AI datasheet(51/251 Pages) STMICROELECTRONICS

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DS12931 Rev 1

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STM32H757xI

Functional overview

3.39

Management Data Input/Output (MDIO) slaves

The devices embed an MDIO slave interface it includes the following features:

•

32 MDIO Registers addresses, each of which is managed using separate input and

output data registers:

–

32 x 16-bit firmware read/write, MDIO read-only output data registers

–

32 x 16-bit firmware read-only, MDIO write-only input data registers

•

Configurable slave (port) address

•

Independently maskable interrupts/events:

–

MDIO Register write

–

MDIO Register read

–

MDIO protocol error

•

Able to operate in and wake up from Stop mode

3.40

SD/SDIO/MMC card host interfaces (SDMMC)

Two SDMMC host interfaces are available. They support MultiMediaCard System

Specification Version 4.51 in three different databus modes: 1 bit (default), 4 bits and 8 bits.

Both interfaces support the SD memory card specifications version 4.1. and the SDIO card

specification version 4.0. in two different databus modes: 1 bit (default) and 4 bits.

Each SDMMC host interface supports only one SD/SDIO/MMC card at any one time and a

stack of MMC Version 4.51 or previous.

The SDMMC host interface embeds a dedicated DMA controller allowing high-speed

transfers between the interface and the SRAM.

3.41

Controller area network (FDCAN1, FDCAN2)

The controller area network (CAN) subsystem consists of two CAN modules, a shared

message RAM memory and a clock calibration unit.

Both CAN modules (FDCAN1 and FDCAN2) are compliant with ISO 11898-1 (CAN protocol

specification version 2.0 part A, B) and CAN FD protocol specification version 1.0.

FDCAN1 supports time triggered CAN (TT-FDCAN) specified in ISO 11898-4, including

event synchronized time-triggered communication, global system time, and clock drift

compensation. The FDCAN1 contains additional registers, specific to the time triggered

feature. The CAN FD option can be used together with event-triggered and time-triggered

CAN communication.

A 10-Kbyte message RAM memory implements filters, receive FIFOs, receive buffers,

transmit event FIFOs, transmit buffers (and triggers for TT-FDCAN). This message RAM is

shared between the two FDCAN1 and FDCAN2 modules.

The common clock calibration unit is optional. It can be used to generate a calibrated clock

for both FDCAN1 and FDCAN2 from the HSI internal RC oscillator and the PLL, by

evaluating CAN messages received by the FDCAN1.

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