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STM32H757AI 数据表(PDF) 183 Page - STMicroelectronics |
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STM32H757AI 数据表(HTML) 183 Page - STMicroelectronics |
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183 / 251 page  DS12931 Rev 1 183/251 STM32H757xI Electrical characteristics 230 Figure 41. SDRAM write access waveforms Table 94. SDRAM Write timings(1) 1. Guaranteed by characterization results. Symbol Parameter Min Max Unit tw(SDCLK) FMC_SDCLK period 2Tfmc_ker_ck – 1 2Tfmc_ker_ck+0.5 ns td(SDCLKL _Data) Data output valid time - 1 th(SDCLKL _Data) Data output hold time 0 - td(SDCLKL_Add) Address valid time - 1.5 td(SDCLKL_SDNWE) SDNWE valid time - 1.5 th(SDCLKL_SDNWE) SDNWE hold time 0.5 - td(SDCLKL_ SDNE) Chip select valid time - 1.5 th(SDCLKL-_SDNE) Chip select hold time 0.5 - td(SDCLKL_SDNRAS) SDNRAS valid time - 1 th(SDCLKL_SDNRAS) SDNRAS hold time 0.5 - td(SDCLKL_SDNCAS) SDNCAS valid time - 1 td(SDCLKL_SDNCAS) SDNCAS hold time 0.5 - MS32752V2 Row n Col1 FMC_SDCLK FMC_A[12:0] FMC_SDNRAS FMC_SDNCAS FMC_SDNWE FMC_D[31:0] FMC_SDNE[1:0] td(SDCLKL_AddR) td(SDCLKL_AddC) th(SDCLKL_AddR) th(SDCLKL_AddC) td(SDCLKL_SNDE) td(SDCLKL_Data) th(SDCLKL_Data) Col2 Coli Coln Data2 Datai Datan Data1 th(SDCLKL_SNDE) td(SDCLKL_NRAS) td(SDCLKL_NCAS) th(SDCLKL_NCAS) th(SDCLKL_NRAS) td(SDCLKL_NWE) th(SDCLKL_NWE) FMC_NBL[3:0] td(SDCLKL_NBL) |
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