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STM32U545NET3QTR 数据表(PDF) 246 Page - STMicroelectronics |
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STM32U545NET3QTR 数据表(HTML) 246 Page - STMicroelectronics |
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246 / 283 page  Electrical characteristics STM32U545xx 246/283 DS14216 Rev 1 Figure 49. PSSI transmit timing diagram MSv63437V1 ts(RDY) tho(DATA) tv(DATA) CKPOL=0 CKPOL=1 PSSI D[15:0] (output) th(RDY) tw(PDCKL) tw(PDCKH) tc(PDCK) tf(PDCK) Invalid data OUT Valid data OUT DEPOL=0 DEPOL=1 RDYPOL=0 RDYPOL=1 Invalid data OUT tr(PDCK) tv(DE) tho(DE) Table 122. PSSI receive characteristics(1) Symbol Parameter Conditions Min Max Unit - Frequency ratio DCMI_PDCK/fHCLK -- 0.4 - PSSI_PDCK PSSI clock input 1.71 V ≤ VDD ≤ 3.6 V - 64 MHz DPIXEL PSSI clock input duty cycle - 30 70 % tSU(DATA) Data input setup time 1.71 V ≤ VDD ≤ 3.6 V 2- ns tH(DATA) Data input hold time 1.5 - tSU(DE) DE input setup time 0.5 - tH(DE) DE input hold time 2 - tOV(RDY) RDY output valid time - 12 tOH(RDY) RDY output hold time 6 - 1. Evaluated by characterization. Not tested in production. |
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