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STM32U545NET3QTR 数据表(PDF) 248 Page - STMicroelectronics |
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STM32U545NET3QTR 数据表(HTML) 248 Page - STMicroelectronics |
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248 / 283 page  Electrical characteristics STM32U545xx 248/283 DS14216 Rev 1 5.3.32 Delay block characteristics Unless otherwise specified, the parameters given in the table below are derived from tests performed under the ambient temperature, fHCLK frequency and VDD supply voltage conditions summarized in Table 33. Table 124. IWDG min/max timeout period at 32 kHz (LSI)(1) Prescaler divider PR[2:0] bits Min timeout RL[11:0] = 0x000 Max timeout RL[11:0] = 0xFFF Unit /4 0 0.125 512 ms /8 1 0.250 1024 /16 2 0.500 2048 /32 3 1.0 4096 /64 4 2.0 8192 /128 5 4.0 16384 /256 6 or 7 8.0 32768 1. The exact timings still depend on the phasing of the APB interface clock versus the LSI clock, so that there is always a full RC period of uncertainty. Table 125. WWDG min/max timeout value at 160 MHz (PCLK) Prescaler WDGTB Min timeout value Max timeout value Unit 1 0 0.025 1.638 ms 2 1 0.051 3.276 4 2 0.102 6.553 8 3 0.204 13.107 16 4 0.409 26.214 32 5 0.819 52.428 46 6 1.177 75.366 128 7 3.276 209.715 Table 126. Delay block characteristics(1) Symbol Parameter Conditions Min Typ Max Unit tinit Initial delay - 350 750 1550 ps t∆ Unit delay - 34 41 51 1. Evaluated by characterization. Not tested in production. |
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