AM79C874VC datasheet(16/60 Pages) AMD

16 / 60 page

Am79C874

P R E L I M INARY

s RXD (receive data) is a nibble (4 bits) of data that is

sampled by the reconciliation sublayer synchro-

nously with respect to RX_CLK. For each RX_CLK

period which RX_DV is asserted, RXD[3:0] are

transferred from the PHY to the MAC reconciliation

sublayer.

s RX_CLK (receive clock) output to the MAC reconcil-

iation sublayer is a continuous clock (during LINK

only) that provides the timing reference for the

transfer of the RX_DV, RXD, and RX_ER signals.

s RX_DV (receive data valid) input from the PHY to in-

dicate the PHY is presenting recovered and de-

coded nibbles to the MAC reconciliation sublayer.

To interpret a receive frame correctly by the recon-

ciliation sublayer, RX_DV must encompass the

frame starting no later than the Start-of-Frame de-

limiter and excluding any End-Stream delimiter.

s RX_ER (receive error) transitions synchronously

with respect to RX_CLK. RX_ER will be asserted

for 1 or more clock periods to indicate to the recon-

ciliation sublayer that an error was detected some-

where in the frame being received by the PHY.

s CRS (carrier sense) is asserted by the PHY when

either the transmit or receive medium is non-idle

and deasserted by the PHY when the transmit and

receive medium are idle.

7-Wire (GPSI) Mode

7-Wire (GPSI) mode uses the existing MII pins, but

data is transferred only on TXD[0] and RXD[0]. This

mode is used in a General Purpose Serial Interface

(GPSI) configuration for 10BASE-T. If the GPIO[0] pin

is LOW at the rising edge of reset, then GPSI mode is

selected. For this configuration, TX_CLK runs at 10

MHz. When the cable is unplugged, 10TXCLK ceases

operation.

The MII pins that relate to 7-wire (GPSI) mode are

shown in Table 1. The unused input pins in this mode

should be tied to ground through a 1 k

W resistor. The

RPTR pin must be connected to GND.

Table 1.

MII Pins That Relate to 10 Mbps

7-Wire (GPSI) Mode

Note: CRS ends one and one-half bit times after the

last data bit. The effect is one or two dribbling bits on

every packet. All MACs truncate packets to eliminate

the dribbling bits. The only noticeable effect is that all

CRC errors are recorded as framing errors.

Use the TECH_SEL[2:0] to select the desired 10BASE-

T operation. For example, to auto-negotiate between

Full Duplex and Half Duplex at 10 Mbps, set ANEG=1

and TECH[2:0]=101.

5B Symbol Mode

The purpose of the 5B Symbol mode is to provide a

way for the MAC to do the 4B/5B encoding/decoding

and scrambling/descrambling in 100 Mbps operation.

This is useful in MAC similar to the Intel/DEC 21143

MAC.

In 10 Mbps operation, the MII signals are not used. In-

stea d, th e Ne tPHY-1LP dev ic e operates as a

10BASE-T transceiver, providing received data to the

MAC over a serial differential pair (see Pin Descrip-

tions, PCSBP pin). The MAC uses two serial differential

pairs to provide transmit data to the NetPHY-1LP de-

vice, where the two differential pairs are combined in

the NetPHY-1LP device to compensate for inter-symbol

interference on the twisted pair medium.

100BASE-X Block

The functions performed by the device include encod-

ing of MII 4-bit data (4B/5B), decoding of received code

groups (5B/4B), generating carrier sense and collision

detect indications, serialization of code groups for

transmission, de-serialization of serial data upon re-

ception, mapping of transmit, receive, carrier sense,

and collision at the MII interface, and recovery of clock

from the incoming data stream. It offers stream cipher

scrambling and descrambling capability for 100BASE-

TX applications.

In th e t r an s m i t da ta pa th fo r 1 0 0 M b p s, th e

NetPHY-1LP transceiver receives 4-bit (nibble) wide

data across the MII at 25 million nibbles per second.

For 100BASE-TX applications, it encodes and scram-

bles the data, serializes it, and transmits an MLT-3 data

stream to the media via an isolation transformer. For

100BASE-FX applications, it encodes and serializes

the data and transmits a Pseudo-ECL (PECL) data

stream to the fiber optic transmitter. See Figure 1.

In the receive data path for 100 Mbps, the NetPHY-1LP

transceiver receives an MLT-3 data stream from the

network. For 100BASE-TX, it then recovers the clock

from the data stream, de-serializes the data stream,

and descrambles/decodes the data stream (5B/4B) be-

fore presenting it at the MII interface.

MII Pin Name

7-Wire (GPSI)

TX_CLK/10TXCLK

Transmit Clock

TXD[0]/10TXD

Transmit Serial Data Stream

TXD[3:1]

Not used

TX_EN/10TXEN

Transmit Enable

TX_ER

Not used

RX_CLK/10RXCLK

Receive Clock

RXD[0] /10RXD

Receive Serial Data Stream

RXD[3:1]

Not used

COL/10COL

Collision Detect

RX_ER

Not used

CRS/10CRS

Carrier Sense Detect

MII Pin Name

7-Wire (GPSI)

AM79C874VC 数据表(PDF) 16 Page - Advanced Micro Devices

AM79C874VC 数据表(HTML) 16 Page - Advanced Micro Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

数据表下载

链接网址

AM79C874VC 数据表(PDF) 16 Page - Advanced Micro Devices

AM79C874VC 数据表(HTML) 16 Page - Advanced Micro Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

数据表 下载

链接网址

数据表下载