AM79C874VC datasheet(23/60 Pages) AMD

23 / 60 page

Am79C874

P R E L I M INARY

sent). The PCS Control block also asserts the COL pin

at the MII and sets the Jabber Detect bit in MII Register

1. Once the internal transmit data stream from the

MENDEC stops, an unjab time of 250-750 ms will

elapse before this block causes the PCS Control block

to de-assert the COL indication and re-enable the

transmit circuitry.

When jabber is detected, this block causes the PCS

control block to assert the COL pin and allows the PCS

Control block to assert or de-assert the CRS pin to in-

dicate the current state of the RX± pair. If there is no re-

ceive activity on RX±, this block causes the PCS

Control block to assert only the COL pin at the MII. If

there is RX± activity, this block causes the PCS Control

block to assert both COL and CRS at the MII. The Jab-

ber function can be disabled by setting MII Register 21,

bit 12.

Reverse Polarity Detection and Correction

Proper 10BASE-T receiver operation requires that the

differential input signal be the correct polarity. That is,

the RX+ line is connected to the RX+ input pin, and the

RX- line is connected to the RX- input pin. Improper

setup of the external wiring can cause the polarity to be

reversed. The NetPHY-1LP receiver has the ability to

detect the polarity of the incoming signal and compen-

sate for it. Thus, the proper signal will appear on the

MDI regardless of the polarity of the input signals.

The internal polarity detection and correction circuitry

is set during the reception of the normal link pulses

(NLP) or packets. The receiver detects the polarity of

the input signal on the first NLP. It locks the polarity cor-

rection circuitry after the reception of two consecutive

packets. The state of the polarity correction circuitry is

locked as long as link is established.

Auto-Negotiation and Miscellaneous

Functions

Auto-Negotiation

The NetPHY-1LP device has the ability to negotiate its

mode of operation over the twisted pair using the Auto-

Negotiation mechanism defined in Clause 28 of the

IEEE 802.3u specification. Auto-Negotiation may be

enabled or disabled by hardware (ANEGA, pin 56) or

software (MII Register 0, bit 12) control (see Table 3).

The NetPHY-1LP device will automatically choose its

mode of operation by advertising its abilities and com-

paring them with those received from its link partner

whenever Auto-Negotiation is enabled.

The content of MII Register 4 is sent to the link partner

during Auto-Negotiation, coded in Fast Link Pulses

(FLPs). MII Register 4, bits 8:5 reflect the state of the

TECH_SEL[2:0] pins after reset.

After reset, software can change any of these bits from

1 to 0 and back to 1, but not from 0 to 1 via the man-

agement interface. Therefore, hardware settings have

priority over software. A write to Register 4 does not

cause the device to restart Auto-Negotiation.

When Auto-Negotiation is enabled, the NetPHY-1LP

device sends FLP during the one of the following con-

ditions: (a) power on, (b) link loss, or (c) restart com-

mand. At the same time, the device monitors incoming

data to determine its mode of operation. When the de-

vice receives a burst of FLPs from its link partner with

three identical link code words (ignoring acknowledge

bit), it stores these code words in MII Register 5 and

waits for the next three identical code words. Once the

device detects the second code word, it will configure

itself to the highest technology that is common to both

ends. The technology priorities are: (1) 100BASE-TX,

full-duplex, (2) 100BASE-TX, half-duplex, (3) 10BASE-

T, full-duplex, and (4) 10BASE-T half-duplex.

Parallel Detection

The parallel detection circuit is enabled as soon as ei-

ther 10BASE-T idle or 100BASE-TX idle is detected.

The mode of operation gets configured based on the

technology of the incoming signal. The NetPHY-1LP

device can also check for a 10BASE-T NLP or

100BASE-TX idle symbol. If either is detected, the de-

vice automatically configures to match the detected op-

erating speed in half-duplex mode. This ability allows

the device to communicate with legacy 10BASE-T and

100BASE-TX systems.

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