AM79C874VC datasheet(15/60 Pages) AMD

15 / 60 page

Am79C874

P R E L I M INARY

FUNCTIONAL DESCRIPTION

The NetPHY-1LP device integrates the 100BASE-X

PCS, PMA, and PMD functions and the 10BASE-T

Manchester ENDEC and transceiver functions in a sin-

gle chip for Ethernet 10 Mbps and 100 Mbps opera-

tions. It performs 4B/5B, MLT3, NRZI, and Manchester

encoding and decoding, clock and data recovery,

stream cipher scrambling/descrambling, adaptive

equalization, line transmission, carrier sense and link

integrity monitor, Auto-Negotiation, and MII manage-

ment functions. It provides an IEEE 802.3u compatible

Media Independent Interface (MII) to communicate

with an Ethernet Media Access Controller (MAC). Se-

lection of 10 Mbps or 100 Mbps operation is based on

settings of internal Serial Management Interface regis-

ters or determined by the on-chip Auto-Negotiation

logic. The device can be set to operate either in full-du-

plex mode or half-duplex mode for either 10 Mbps or

100 Mbps.

The NetPHY-1LP device communicates with a re-

peater, switch, or MAC device through either the Media

Independent Interface (MII) or the 10 Mbps 7-wire

(GPSI) interface.

The NetPHY-1LP device consists of the following func-

tional blocks:

s MII Mode

s 7-Wire (GPSI) Mode

s PCS Bypass (5B Symbol) Mode

s 100BASE-X Block including:

— Transmit Process

— Receive Process

— 4B/5B Encoder and Decoder

— Scrambler and Descrambler

— Link Monitor

— MLT-3

— Adaptive Equalizer

— Baseline Wander Compensation

— Clock/Data Recovery

— PLL Clock Synthesizer

s 10BASE-T Block including:

— Transmit Process

— Receive Process

— Interface Status

— Collision Detect

— Jabber

— Reverse Polarity Detection and Correction

s Auto-Negotiation and miscellaneous functions in-

cluding:

— Auto-Negotiation

— Parallel Detection

— Far-End Fault

— SQE (Heartbeat)

— Loopback Operation

— Reset

s LED Port Configuration

s Power Savings Mechanisms including:

— Selectable Transformer

— Power Down

— Unplugged

— Idle Wire

s PHY Control and Management

Modes of Operation

The MII/GPSI/5B Symbol interface provides the data

path connection between the NetPHY-1LP transceiver

and the Media Access Controller (MAC), repeater, or

switch. The MDC and MDIO pins are responsible for

communication between the NetPHY-1LP transceiver

and the station management entity (STA). The MDC

and MDIO pins can be used in any mode of operation.

MII Mode

The purpose of the MII mode is to provide a simple,

easy to implement connection between the MAC Rec-

onciliation layer and the PHY. The MII is designed to

make the differences between various media transpar-

ent to the MAC sublayer.

The MII consists of a nibble wide receive data bus, a

nibble wide transmit data bus, and control signals to fa-

cilitate data transfers between the PHY and the Recon-

ciliation layer.

s TXD (transmit data) is a nibble (4 bits) of data that

are driven by the reconciliation sublayer synchro-

nously with respect to TX_CLK. For each TX_CLK

period which TX_EN is asserted, TXD[3:0] are ac-

cepted for transmission by the PHY.

s TX_CLK (transmit clock) output to the MAC recon-

ciliation sublayer is a continuous clock that provides

the timing reference for the transfer of the TX_EN,

TXD, and TX_ER signals.

s TX_EN (transmit enable) input from the MAC recon-

ciliation sublayer to indicate nibbles are being

presented on the MII for transmission on the physi-

cal medium. TX_ER (transmit coding error) transi-

tions synchronously with respect to TX_CLK. If

TX_ER is asserted for one or more clock periods,

and TX_EN is asserted, the PHY will emit one or

more symbols that are not part of the valid data de-

limiter set somewhere in the frame being transmit-

ted.

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