AM79C874VC datasheet(30/60 Pages) AMD

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Am79C874

P R E L I M INARY

MII Management Control Register (Register 0)

Table 10.

MII Management Control Register (Register 0)

Reg

Bit

Name

Description

Read/

Write

Default

Reset

1 = PHY reset.

0 = Normal operation.

This bit is self-clearing.

RW/SC

Loopback

1 = Enable loopback mode. This will loopback TXD to RXD, thus it

will ignore all the activity on the cable media. During loopback, a

10-Mbps link is sent to the link partner (Register 21, bit 14 is forced.)

0 = Disable Loopback mode. Normal operation.

Speed Select

1 = 100 Mbps, 0 = 10 Mbps. This bit will be ignored if Auto

Negotiation is enabled (0.12 = 1).

Refer to Table 3 to determine when this bit can be changed.

Set by

TECH[2:0]

pins

012

Auto-Neg

Enable

1 = Enable auto-negotiate process (overrides 0.13 and 0.8).

0 = Disable auto-negotiate process. Mode selection is controlled via

bit 0.8, 0.13 or through TECH[2:0] pins.

Refer to Table 3 to determine when this bit can be changed.

Set by

ANEGA

011

Power Down

1 = Power down. The NetPHY-1LP device will shut off all blocks

except for MDIO/MDC interface. Setting PWRDN pin to high will

achieve the same result.

0 = Normal operation.

010

Isolate

1 = Electrically isolate the PHY from MII. However, PHY is still able

to respond to MDC/MDIO. The default value of this bit depends on

ISODEF pin, i.e., ISODEF=1, ISO bit will set to 1, & ISODEF=0, ISO

bit will set to 0.

0 = Normal operation.

Set by

ISODEF

Restart Auto-

Negotiation

1 = Restart Auto-Negotiation process.

0 = Normal operation.

RW/SC

Duplex Mode

1 = Full duplex, 0 = Half duplex.

Refer to Table 3 to determine when this bit can be changed.

Set by

TECH[2:0]

pins

Collision Test

1 = Enable collision test, which issues the COL signal in response

to the assertion of TX_EN signal. Collision test is disabled if PCSBP

pin is high. Collision test is enabled regardless of the duplex mode.

0 = disable COL test.

6:0

Reserved

Write as 0, ignore when read.

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