AM79C874VC datasheet(24/60 Pages) AMD

24 / 60 page

Am79C874

P R E L I M INARY

Table 3.

Speed and Duplex Capabilities

Notes:

1. MII Register 0 (speed and duplex bits) must be set by the MAC to achieve a link.

2. The advertised abilities in MII Register 4 cannot exceed the abilities of MII Register 1. Auto-Negotiation should always remain

enabled.

3. When Auto-Negotiation is enabled, these bits can be written but will be ignored by the PHY.

Far-End Fault

Auto-Negotiation provides a remote fault capability for

detecting asymmetric link failure. Since 100Base-FX

systems do not use Auto-Negotiation, an alternative,

in-band signaling scheme, Far-End Fault is used to sig-

nal remote fault conditions. Far-End Fault is a stream of

63 consecutive 1s followed by one logic 0. This pattern

is repeated three times. A Far-End Fault will be sig-

naled under three conditions: (1) when no activity is re-

ceived from the link partner, (2) when the clock

recovery circuit detects signal error or PLL lock error,

and (3) when the management entity sets the transmit

FEF bit (MII Register 21, bit 7).

The Far-End Fault mechanism defaults to enable

100BASE-FX mode and disable 100BASE-TX and

10BASE-T modes, and may be controlled by software

after reset.

SQE (Heartbeat)

When the SQE test is enabled, a COL signal with a 5-

15 bit time pulse will be issued after each transmitting

packet. SQE is enabled and disabled via MII Register

16, bit 11.

Loopback Operation

A local loopback and remote loopback are provided for

testing. They can be enabled by writing to either MII

(EN_RPBK).

The local loopback routes transmitted data at the out-

put of NRZ-to-NRZI conversion module back to the

receiving path’s clock and data recovery module for

connection to PCS in 5 bits symbol format. This loop-

back is used to check all the connections at the 5-bit

symbol bus side and the operation of analog phase

locked loop. In local loopback, the SD output is forced

to logic one and TX± outputs are tristated.

During local loopback, a 10-Mbps link is sent to the link

partner. In either 100BASE-TX or 10BASE-T loopback

mode, the link for 10 Mbps is forced (Register 21, bit

14) and is seen externally. If packets are transmitted

from the Device Under Test (DUT), the link between the

DUT and link partner is lost. Ceasing transmission

causes the link to go back up.

In remote loopback, incoming data passes through the

equalizer and clock recovery, then loop back to NRZI/

MLT3 conversion module and out to the driver. This

loopback is used to check the device’s connection on

the media side and the operation of its internal adaptive

equalizer, phase-locked loop, and digital wave shape

synthesizer. During remote loopback, signal detect

(SD) output is forced to logic zero. Note that remote

loopback operates only in 100BASE-TX mode.

ANEGA

Tech[2]

Tech[1]

Tech[0]

Speed

Duplex

ANEG-EN

Capabilities/ANEG

(Hardwired on Board)

(Changeable in MII Register 0)

Yes (Note 1)

All Capabilities

10HD

100HD

Yes (Note 1)

All Capabilities

10FD

100FD

Yes (Note 3)

Yes (Note 2)

No Capabilities, ANEG

Yes (Note 3)

Yes (Note 2)

10HD, ANEG

Yes (Note 3)

Yes (Note 2)

100HD, ANEG

Yes (Note 3)

Yes (Note 2)

100HD, 10HD, ANEG

Yes (Note 3)

Yes (Note 2)

No Capabilities, ANEG

Yes (Note 3)

Yes (Note 2)

10FD/HD, ANEG

Yes (Note 3)

Yes (Note 2)

100FD/HD, ANEG

Yes (Note 2)

Yes (Note 3)

Yes (Note 2)

All Capabilities, ANEG

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