AM79C874VC datasheet(13/60 Pages) AMD

13 / 60 page

Am79C874

P R E L I M INARY

MDC

Management Data Clock

Input

This clock is sourced by the MAC and is used to

synchronize MDIO data. When management is not

used, this pin should be tied to ground.

INTR

Interrupt

Output, High Impedance

This pin is used to signal an interrupt to the MAC. The

pin will be forced high or low (normally high impedance)

to signal an interrupt depending upon the value of the

INTR_LEVL bit, MII Register 16, bit 14. The events

which trigger an interrupt can be programmed via the

Interrupt Control Register (Register 17).

TECH_SEL[2:0]

Technology Select

Input, Pull-Up

The Technology Select pins, in conjunction with the

ANEGA pin, set the speed and duplex configurations

for the device on the rising edge of reset. These capa-

bilities are reflected in MII Register 1 and MII Register

4. Table 3 lists the possible configurations for the de-

vice.

If the input is listed as LOW, the pin should be

pulled to ground via a 10 k

W resistor on the rising edge

of reset. If the input is listed as HIGH, the pin can be left

unconnected.

Note: By

using

resistors

hard

wire

the

TECH_SEL[2:0] pins and the ANEGA pin, using the

MDC/MDIO management interface pins becomes op-

tional. The device’s speed, duplex, and auto-negotia-

t i on capabilit ies are set via ha r d w a re. If the

management interface is used, the registers cannot be

set to a higher capability than the hard-wired setting.

The highest capabilities are Full Duplex, 100 Mbps,

and Auto-Negotiation enabled.

ANEGA

Auto-Negotiation Ability

Input, Pull-Up

When this pin is pulled to ground via a 10 k

W resistor,

on the rising edge of reset, Auto-Negotiation is dis-

abled. When this pin is left unconnected, on the rising

edge of reset, Auto-Negotiation is enabled. Note that

this pin acts in conjunction with Tech_Sel[2:0] on the

rising edge of reset. Refer to Table 3 to determine the

desired configuration for the device.

Note: By

using

resistors

hard

wire

the

TECH_SEL[2:0] pins and the ANEGA pin, using the

MDC/MDIO management interface pins becomes op-

tional. The device’s speed, duplex, and auto-negotia-

t i on capabilit ies are set via ha r d w a re. If the

management interface is used, the registers cannot be

set to a higher capability than the hard-wired setting.

The highest capabilities are Full Duplex, 100 Mbps,

and Auto-Negotiation enabled.

RPTR

Repeater Mode

Input

This pin should be tied to ground via a 10 k

W resistor if

repeater mode is to be disabled. When this pin is pulled

high via a 10 k

W resistor, repeater mode will be en-

abled. Repeater mode can also enabled via MII Regis-

ter 16, bit 15.

LED Port Pins

LEDRX/LED_SEL

Receive LED/LED Configuration Select

Input/Output, Pull-Up

When this pin is pulled low via a 5 k

W resistor, on the

rising edge of reset, the advanced LED configuration is

enabled. If there is no pull-down resistor present, on

the rising edge of reset, the standard LED configuration

is enabled.

After the rising edge of reset this pin controls the Re-

ceive LED. This pin toggles between high and low when

data is received. When the device is operating in the

standard LED mode, refer to Table 4 and Figure 5 in the

LED Port Configuration section. When the device is op-

erating in the advanced LED mode, refer to Table 5 and

Figure 6 in the LED Port Configuration section.

LEDCOL/SCRAM_EN

Collision LED/Scrambler Enable

Input/Output, Pull-Up

When this pin is pulled low via a 1-k

W resistor, on the

rising edge of reset, the scrambler/descrambler is dis-

abled. If no pull-down resistor is present, on the rising

edge of reset, the scrambler/descrambler is enabled.

After the rising edge of reset this pin controls the Colli-

sion LED. This pin toggles between high and low when

there is a collision in half-duplex operation. In full-

duplex operation this pin is inactive. When the device is

operating in the standard LED mode (see LEDRX/LED-

SEL pin description), refer to Table 4 and Figure 5 in the

LED Port Configuration section. When the device is op-

erating in the advanced LED mode (see LEDRX/LED-

SEL pin description), see Table 5 and Figure 6.

LEDLNK/LED_10LNK/LED_PCSBP_SD

Link LED/7-Wire Link LED/PCSBP Signal Detect

Output

Whe n a link is esta blishe d in 100 BASE-X o r

10BASE-T mode, this pin will assume a logic low level.

When a link is established in 7-Wire mode, this pin will

assume a logic high level.

When in PCS Bypass mode, this pin assumes a logic

high level indicating Signal Detect.

Refer to Table 4 and Figure 4 in the LED Port Configu-

ration section if the device is operating in the standard

LED mode. See Table 5 and Figure 5 if the device is op-

erating in the advanced LED mode.

AM79C874VC 数据表(PDF) 13 Page - Advanced Micro Devices

AM79C874VC 数据表(HTML) 13 Page - Advanced Micro Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

数据表下载