AM79C874VC datasheet(29/60 Pages) AMD

29 / 60 page

Am79C874

P R E L I M INARY

Bad Management Frame Handling

The management block of the device can recognize

management frames without preambles (preamble

suppression). However, if it receives a bad manage-

ment frame, it will go into a Bad Management Frame

state. It will stay in this state and will not respond to any

management frame without preambles until a frame

with a full 32-bit preamble is received, then it will return

to normal operation.

A bad management frame is a frame that does not

comply with the IEEE standard specification. It can be

one with less than 32-bit preamble, with illegal OP field,

etc. However, a frame with more than 32 preamble bits

is considered to be a good frame.

After a reset, the NetPHY-1LP device requires a mini-

mum preamble of 32 bits before management data

(MDIO) can be received. After that, the management

data being received by the NetPHY-1LP device does

not require a preamble.

The following registers given in Table 8 are supported

(register addresses are in decimal).

Table 8.

The Physical Address of the PHY is set using the pins

defined as PHYAD[4:0]. These input signals are

strapped externally and sampled as when reset goes

high. The PHYAD pins can be reprogrammed via soft-

ware.

Serial Management Registers

A detailed definition of each Serial Management regis-

ter follows. The mode legend is shown in Table 9.

Table 9.

Legend for Register Table

Address

(in

Decimal)

Description

MII Management Control Register

MII Management Status Register

PHY Identifier 1 Register

PHY Identifier 2 Register

Auto-Negotiation Advertisement Register

Auto-Negotiation Link Partner Ability Register

Auto-Negotiation Expansion Register

Next Page Advertisement Register

8-15

Reserved

Miscellaneous Features Register

Interrupt Control/Status Register

Diagnostic Register

Power Management & Loopback Register

Reserved

Mode Control Register

Reserved

Disconnect Counter

Receive Error Counter

25-31

Reserved

Type

Description

Readable and writable

Self Clearing

Latch Low until clear

Read Only

Cleared on the read operation

Latch high until clear

AM79C874VC 数据表(PDF) 29 Page - Advanced Micro Devices

AM79C874VC 数据表(HTML) 29 Page - Advanced Micro Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

数据表下载

链接网址

AM79C874VC 数据表(PDF) 29 Page - Advanced Micro Devices

AM79C874VC 数据表(HTML) 29 Page - Advanced Micro Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

数据表 下载

链接网址

数据表下载