AM79C874VC datasheet(36/60 Pages) AMD

36 / 60 page

Am79C874

P R E L I M INARY

Miscellaneous Features Register (Register 16)

Table 19.

Miscellaneous Features Register (Register 16)

Reg

Bit

Name

Description

Read/

Write

Default

Repeater

1= Repeater mode, full-duplex is inactive, and CRS only responds

to receive activity. SQE test function is also disabled.

Set by

RPTR

INTR_LEVL

INTR will be active high if this register bit is set to 1. Pin requires

an external pull-down resistor.

INTR will be active low if this register bit is set to 0. Pin requires

an external pull-up resistor.

13:12

Reserved

Write as 0, ignore when read.

SQE Test Inhibit

1 = Disable 10BASE-T SQE testing.

0 = Enable 10BASE-T SQE testing. A COL pulse is generated

following the completion of a packet transmission.

10BASE-T

Loopback

1 = Enable normal loopback in 10BASE-T mode.

0 = Disable normal loopback in 10BASE-T mode.

GPIO_1 Data

When GPIO_1 DIR bit is set to 1, this bit reflects the value of the

GPIO[1] pin. When GPIO_1 DIR bit is set to 0, the value of this bit

will be presented on the GPIO[1] pin.

GPIO_1 DIR

1 = GPIO[1] pin is an input.

0 = GPIO[1] pin is an output.

GPIO_0 Data

When GPIO_0 DIR bit is set to 1, this bit reflects the value of the

GPIO[0] pin. When GPIO[0] DIR bit is set to 0, the value of this bit

will be presented on the GPIO[0] pin.

GPIO_0 DIR

1 = GPIO[0] pin is an input.

0 = GPIO[0] pin is an output.

Auto polarity

Disable

1 = Disable auto polarity detection/correction.

0 = Enable auto polarity detection/correction.

Reverse Polarity

When Register 16.5 is set to 0, this bit will be set to 1 if reverse

polarity is detected on the media. Otherwise, it will be 0.

When Register 16.5 is set to 1, writing a 1 to this bit will reverse

the polarity of the transmitter.

Note: Reverse polarity is detected either through eight inverted

NLPs or through a burst of an inverted FLP.

3:1

Reserved

Write as 0, ignore when read.

Receive Clock

Control

Writing a 1 to this bit will shut off RX_CLK when incoming data is

not present and only if there is LINK present. RX_CLK will resume

activity one clock cycle prior to RX_DV going high, and shut off 64

clock cycles after RX_DV goes low.

A 0 indicates that RX_CLK runs continuously during LINK

whether data is received or not

In loopback and PCS bypass modes, writing to this bit does not

affect RX_CLK. Receive clock will be constantly active.

AM79C874VC 数据表(PDF) 36 Page - Advanced Micro Devices

AM79C874VC 数据表(HTML) 36 Page - Advanced Micro Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

数据表下载