ADE7169F16 datasheet(42/140 Pages) AD

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ADE7169F16

Preliminary Technical Data

Rev. PrD | Page 42 of 140

V1P

V1N

VIN

⋅ V

GAIN[7:0]

GAIN (K)

SELECTION

Figure 16. PGA in current channel

In addition to the PGA, Channel 1 also has a full-scale input

range selection for the ADC. The ADC analog input range

selection is also made using the gain register—see Figure 17. As

mentioned previously, the maximum differential input voltage is

0.5 V.

RESERVED

GAIN REGISTER*

CURRENT AND VOLTAGE CHANNELS PGA CONTROL

ADDR:

1BH

* REGISTER CONTENTS

SHOW POWER-ON DEFAULTS

PGA 2 GAIN SELECT

000 = x 1

001 = x 2

010 = x 4

011 = x 8

100 = x 16

PGA 1 GAIN SELECT

000 = x 1

001 = x 2

010 = x 4

011 = x 8

100 = x 16

Figure 17. ADE7169F16 Analog Gain Register

ANALOG TO DIGITAL CONVERSION

The ADE7169F16 has two sigma-delta Analog to Digital

Converters (ADC). The outputs of these ADCs are mapped

directly to waveform sampling SFRs (address 0xE2 to 0xE7) and

are used for the energy measurement internal digital signal

processing. In PSM1 (Battery mode)and PSM2 (Sleep mode),

the ADCs are powered down to minimize power consumption.

For simplicity, the block diagram in Figure 18 shows a first-

order Σ-Δ ADC. The converter is made up of the Σ-Δ

modulator and the digital low-pass filter.

DIGITAL

LOW-PASS

FILTER

ANALOG

LOW-PASS FILTER

–

VREF

1-BIT DAC

INTEGRATOR

MCLK/5

LATCHED

COMPARATOR

.....10100101.....

–

Figure 18. First-Order

Σ-∆ ADC

A Σ-∆ modulator converts the input signal into a continuous

serial stream of 1s and 0s at a rate determined by the sampling

clock. In the ADE7169F16, the sampling clock is equal to

MCLK/5. The 1-bit DAC in the feedback loop is driven by the

serial data stream. The DAC output is subtracted from the input

signal. If the loop gain is high enough, the average value of the

DAC output (and therefore the bit stream) can approach that of

the input signal level. For any given input value in a single

sampling interval, the data from the 1-bit ADC is virtually

meaningless. Only when a large number of samples are averaged

is a meaningful result obtained. This averaging is carried out in

the second part of the ADC, the digital low-pass filter. By

averaging a large number of bits from the modulator, the low-

pass filter can produce 24-bit data-words that are proportional

to the input signal level.

The Σ-Δ converter uses two techniques to achieve high

resolution from what is essentially a 1-bit conversion technique.

The first is oversampling. Oversampling means that the signal is

sampled at a rate (frequency), which is many times higher than

the bandwidth of interest. For example, the sampling rate in the

ADE7169F16 is MCLK/5 (819.2 kHz) and the band of interest is

40 Hz to 2 kHz. Oversampling has the effect of spreading the

quantization noise (noise due to sampling) over a wider

bandwidth. With the noise spread more thinly over a wider

bandwidth, the quantization noise in the band of interest is

lowered — see Figure 19. However, oversampling alone is not

efficient enough to improve the signal-to-noise ratio (SNR) in

the band of interest. For example, an oversampling ratio of 4 is

required just to increase the SNR by only 6 dB (1 bit). To keep

the oversampling ratio at a reasonable level, it is possible to

shape the quantization noise so that the majority of the noise

lies at the higher frequencies. In the Σ-Δ modulator, the noise is

shaped by the integrator, which has a high-pass-type response

for the quantization noise. The result is that most of the noise is

at the higher frequencies where it can be removed by the digital

low-pass filter. This noise shaping is shown in Figure 19.

409.6

819.2

NOISE

SIGNAL

DIGITAL

FILTER

ANTILALIAS

FILTER (RC)

SAMPLING

FREQUENCY

HIGH RESOLUTION

OUTPUT FROM DIGITAL

LPF

SHAPED

NOISE

409.6

819.2

NOISE

SIGNAL

FREQUENCY (kHz)

02875-0-047

Figure 19. Noise Reduction Due to Oversampling and

Noise Shaping in the Analog Modulator

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