ADE7169F16 datasheet(43/140 Pages) AD

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Preliminary Technical Data

ADE7169F16

Rev. PrD | Page 43 of 140

Anti-aliasing Filter

Figure 18 also shows an analog low-pass filter (RC) on the input

to the modulator. This filter is present to prevent aliasing.

Aliasing is an artifact of all sampled systems. Aliasing means

that frequency components in the input signal to the ADC,

which are higher than half the sampling rate of the ADC,

appear in the sampled signal at a frequency below half the

sampling rate. Figure 20 illustrates the effect. Frequency

components (arrows shown in black) above half the sampling

frequency (also know as the Nyquist frequency, i.e., 409.6 kHz)

are imaged or folded back down below 409.6 kHz. This happens

with all ADCs regardless of the architecture. In the example

shown, only frequencies near the sampling frequency, i.e., 819.2

kHz, move into the band of interest for metering, i.e., 40 Hz to 2

kHz. This allows the use of a very simple LPF (low-pass filter)

to attenuate high frequency (near 819.2 kHz) noise, and

prevents distortion in the band of interest. For conventional

current sensors, a simple RC filter (single-pole LPF) with a

corner frequency of 10 kHz produces an attenuation of

approximately 40 dB at 819.2 kHz — see Figure 20. The 20 dB

per decade attenuation is usually sufficient to eliminate the

effects of aliasing for conventional current sensors. However, for

a di/dt sensor such as a Rogowski coil, the sensor has a 20 dB

per decade gain. This neutralizes the –20 dB per decade

attenuation produced by one simple LPF. Therefore, when using

a di/dt sensor, care should be taken to offset the 20 dB per

decade gain. One simple approach is to cascade two RC filters

to produce the –40 dB per decade attenuation needed.

SAMPLING

FREQUENCY

IMAGE

FREQUENCIES

ALIASING EFFECTS

409.6

819.2

FREQUENCY (kHz)

Figure 20. ADC and Signal Processing in current channel Outline Dimensions

ADC Transfer Function

Both ADCs in the ADE7169F16 are designed to produce the

same output code for the same input signal level. With a full-

scale signal on the input of 0.5 V and an internal reference of

1.2 V, the ADC output code is nominally 2,684,354 or 28F5C2h.

The maximum code from the ADC is ±4,194,304; this is

equivalent to an input signal level of ±0.794 V. However, for

specified performance, it is recommended that the full-scale

input signal level of 0.5 V not be exceeded.

Current Channel ADC

Figure 21 shows the ADC and signal processing chain for the

current channel. In waveform sampling mode, the ADC outputs

a signed twos complement 24-bit data-word at a maximum of

25.6 kSPS (MCLK/160). With the specified full-scale analog

input signal of 0.5 V (or 0.25 V or 0.125 V—see the Analog

Inputs section) the ADC produces an output code that is

approximately between 0x28F5C2 (+2,684,354d) and

0xD70A3E (–2,684,354d)—see Figure 21.

x1, x2, x4,

x8, x16

ANALOG

INPUT

RANGE

DIGITAL

INTEGRATOR*

HPF

ADC

REFERENCE

0.5V, 0.25V,

0.125V, 62.5mV,

31.3mV

CURRENT CHANNEL

WAVEFORM

DATA RANGE

ACTIVE AND REACTIVE

POWER CALCULATION

WAVEFORM SAMPLE

CURRENT RMS (IRMS)

CALCULATION

50Hz

IAP

PGA1

{GAIN[2:0]}

*WHEN DIGITAL INTEGRATOR IS ENABLED, FULL-SCALE OUTPUT DATA IS ATTENUATED

DEPENDING ON THE SIGNAL FREQUENCY BECAUSE THE INTEGRATOR HAS A –20dB/DECADE

FREQUENCY RESPONSE. WHEN DISABLED, THE OUTPUT WILL NOT BE FURTHER ATTENUATED.

0xD70A3E

0x000000

0x28F5C2

CURRENT CHANNEL

WAVEFORM

DATA RANGE AFTER

INTEGRATOR (50Hz)

0xCBD330

0x000000

0x342CD0

60Hz

CURRENT CHANNEL

WAVEFORM

DATA RANGE AFTER

INTEGRATOR (60Hz)

0xD487B0

0x000000

0x2B7850

MODE1[5]

HPF

ADC

PGA1

IBP

Figure 21. ADC and Signal Processing in Current Channel

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