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ADE7169F16 数据表(PDF) 44 Page - Analog Devices |
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ADE7169F16 数据表(HTML) 44 Page - Analog Devices |
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44 / 140 page ![]() ADE7169F16 Preliminary Technical Data Rev. PrD | Page 44 of 140 Voltage Channel ADC Figure 21 shows the ADC and signal processing chain for the Voltage Channel. In waveform sampling mode, the ADC outputs a signed twos complement 24-bit data-word at a maximum of 25.6 kSPS (MCLK/160). The ADC produces an output code that is approximately between 0x28F5 (+10,485d) and 0xD70B (–10,485d)—see Figure 22. x1, x2, x4, x8, x16 ANALOG INPUT RANGE HPF ADC REFERENCE V2 0V 0.5V, 0.25V, 0.125V, 62.5mV, 31.3mV WAVEFORM SAMPLE REGISTER VOLTAGE RMS (VRMS) CALCULATION VP PGA2 V2 {GAIN[7:5]} VOLTAGE CHANNEL WAVEFORM DATA RANGE 0xD70B 0x0000 0x28F5 ACTIVE AND REACTIVE POWER CALCULATION LPF1 f–3dB = 63.7Hz MODE1[6] ZX SIGNAL DATA RANGE for 60Hz signal 0xE230 0x0000 0x1DD0 ZX DETECTION ZX SIGNAL DATA RANGE for 50Hz signal 0xDFC9 0x0000 0x2037 VOLTAGE PEAK DETECT Figure 22. ADC and Signal Processing in Voltage Channel Channel Sampling The waveform samples of the current ADC and voltage ADC can also be routed to the waveform registers to be read by the MCU core. The active, reactive, apparent power, and energy calculation remain uninterrupted during waveform sampling. When in waveform sampling mode, one of four output sample rates can be chosen by using Bits 0 and 1 of the WAVMODE register (WAVSEL1,0). The output sample rate can be 25.6 kSPS, 12.8kSPS, 6.4 kSPS, or 3.2 kSPS—see Table 30. If the WFSM enable bit is set in the Interrupt Enable Register 3 SFR (MIRQENH, 0xDB), the 8052 core has a pending ADE interrupt. The sampled signals selected in the WAVMODE register will be latched into the Waveform SFRs when the waveform high byte (WAV1H or WAV2H) is read. The ADE interrupt stays active until the WFSM status bit is cleared—see Energy measurement interrupts section. FAULT DETECTION The ADE7169F16 incorporates a fault detection scheme that warns of fault conditions and allows the ADE7169F16 to continue accurate measurement during a fault event. The ADE7169F16 does this by continuously monitoring both current inputs (IA and IB). These currents will be referred for ease of understanding as phase and neutral (return) currents. In the ADE7169F16, a fault condition is defined when the difference between IA and IB is greater than 6.25% of the active channel. If a fault condition is detected and the inactive channel is larger than the active channel, the ADE7169F16 automatically switches to current measurement to the inactive channel. During a fault, the active, reactive, current rms and apparent powers are generated using the larger of the two currents. On power-up, IA is the current input selected for Active, Reactive, and Apparent power and Irms calculations. To prevent false alarm, averaging is done for the fault detection and a fault condition is detected approximately 1 second after the event. The fault detection is automatically disabled when the voltage signal is less than 0.3% of the full-scale input range. This eliminates false detection of a fault due to noise at light loads. Because the ADE7169F16 looks for a difference between the voltage signals on IA and IB, it is important that both current transducers be closely matched. Channel selection Indication The current channel selected for measurement is indicated by bit 7 (ICHANNEL) in the ACCMODE register (0x0F). When this bit is cleared, IA is selected and when it is set, IB is selected. |
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