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ADE7169F16 数据表(PDF) 24 Page - Analog Devices |
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ADE7169F16 数据表(HTML) 24 Page - Analog Devices |
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24 / 140 page  ADE7169F16 Preliminary Technical Data Rev. PrD | Page 24 of 140 Set when VSW switches from VDD to VBAT. 0 0xF8 FVDC 0 VDCIN Monitor interrupt flag. Set when VDCIN falls below 1.2V. Table 14. Battery Switchover Configuration SFR (BATPR, 0xF5) Bit Location Bit Mnemonic Default Value Description 7-2 Reserved 00 These bits must be kept to 0 for proper operation Control bits for Battery Switchover. BATPRG [1:0] Function 0 0 Battery Swichover Enabled on Low VDD 0 1 Battery Swichover Enabled on Low VDD and Low VDCIN 1-0 BATPRG [1:0] 00 1 X Battery Switchover Disabled Table 15. Peripheral Configuration SFR (PERIPH, 0xF4) Bit Location Bit Mnemonic Default Value Description 7 RXFLAG 0 If set, indicates that a RX Edge event triggered wakeup from PSM2 Indicates the power supply that is connected internally to VSW. 0 VSW=VBAT 6 VSWSOURCE 1 1 VSW=VDD 5 VDD_OK 1 If set, indicates that VDD power supply is ok for operation 4 PLL_FLT 0 If set, indicates that PLL is not locked 3 REF_BAT_EN 0 If set, Internal voltage reference enabled in PSM2 mode. This bit should be set if LCD On in PSM2 mode. 2 Reserved 0 This bit should be kept to zero Controls the function of the P1.0/RX pin. RXPROG [1:0] Function 0 0 GPIO 0 1 RX with wakeup disabled 1-0 RXPROG[1:0] 00 1 1 RX with wakeup enabled Table 16. Power Management Interrupt Enable SFR (IPSME, 0xEC) Bit Location Bit Mnemonic Default Value Description 7 EPSR 0 Enables a PSM interrupt when the Power Supply Restored flag is set. 6 ADEIAUTCLR 0 If set, the ADE interrupt status registers MIRQSTH/M/L registers will be read with reset. 5 ESAG 0 Enables a PSM interrupt when the voltage sag flag (FSAG) is set. 4 RESERVED 0 This bit must be kept cleared for proper operation 3 EVSW 0 Enables a PSM interrupt when the VSW monitor flag (FVSW) is set. 2 EBAT 0 Enables a PSM interrupt when the VBAT monitor flag (FBAT) is set. 1 EBSO 0 Enables a PSM interrupt when the Battery Switchover flag (FBSO) is set. 0 EVDCIN 0 Enables a PSM interrupt when the VDCIN monitor flag (FVDCIN) is set. Table 17. Scratch Pad 1 SFR (SCRATCH1, 0xFB) Bit Location Bit Mnemonic Default Value Description 7-0 SCRATCH1 0 Value can be written/read in this register. This value will be maintained in all the power saving modes of the ADE7169F16 |
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