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ADE7169F16 数据表(PDF) 83 Page - Analog Devices

部件名 ADE7169F16
功能描述  Single-Phase Energy Measurement IC with 8052 MCU, RTC and LCD driver
PDF  140 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADE7169F16 数据表(HTML) 83 Page - Analog Devices

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Preliminary Technical Data
ADE7169F16
Rev. PrD | Page 83 of 140
0
0xA8
EX0
Set by the user to enable External Interrupt 0 (
).
Table 63. Interrupt priority SFR (IP, 0xB8)
Bit Location
Bit
Addr.
Bit Name
Description
7
0xBF
PADE
ADE Energy Measurement Interrupt Priority (1 = High; 0 =
Low).
6
0xBE
PTEMP
Temperature ADC Interrupt Priority (1 = High; 0 = Low).
5
0xBD
PT2
Timer 2 Interrupt Priority (1 = High; 0 = Low).
4
0xBC
PS
UART Serial Port Interrupt Priority (1 = High; 0 = Low).
3
0xBB
PT1
Timer 1 Interrupt Priority (1 = High; 0 = Low).
2
0xBA
PX1
INT1 (External Interrupt 1) priority (1 = High; 0 = Low).
1
0xB9
PT0
Timer 0 Interrupt Priority (1 = High; 0 = Low).
0
0xB8
PX0
INT0 (External Interrupt 0) Priority (1 = High; 0 = Low).
Table 64. Interrupt Enable and Priority 2 SFR (IEIP2, 0xA9)
Bit
Location
Bit
Mnemonic
Description
7
6
PTI
RTC Interrupt Priority (1 = High; 0 = Low).
5
4
PSI
SPI/I2C Interrupt Priority (1 = High; 0 = Low).
3
EADE
Set by the user to enable the Energy Metering Interrupt (ADE)
2
ETI
Set by the user to enable the RTC Interval Timer interrupt.
1
EPSM
Set by the user to enable the PSM Power Supply Management interrupt.
0
ESI
Set by the user to enable the SPI/I2C interrupt.
Table 65. WatchDog Timer SFR (WDCON, 0xC0)
Bit
Location
Bit
Addr.
Bit
Name
Default
Value
Description
7-4
0xC7 –
0xC4
PRE[3:0]
7
Watchdog pre-scaler. In normal mode, the 16-bit watchdog timer is clocked by the
input clock (32.768kHz). The PRE bits set which of the upper bits of the counter are
used as the watchdog output following:
CLKIN
t
PRE
watchdog
9
2
2
×
=
[3:0]
Watchdog Timeout
0000
15.6ms
0001
31.2ms
0010
62.5ms
0011
125ms
0100
250ms
0101
500ms
0110
1s
0111
2s
1000
0
Automatic Reset
1001
0
Serial download reset
1010 to 1111
Not a valid selection
3
0xC3
WDIR
0
Watchdog interrupt response bit.
When clear, watchdog will generate a system reset when the watchdog time out
period has expired
When set, the watchdog will generate a interrupt when the watchdog time out
period has expired.



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