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ADE7169F16

Preliminary Technical Data

Rev. PrD | Page 58 of 140

(default), the VARSIGN flag in the Interrupt Status Register 1

SFR (MIRQSTL, 0xDC) will be set when a transition from

positive to negative reactive power has occurred.

When VARSIGN in the ACCMODE register (0x0F) is set, the

VARSIGN flag in the Interrupt Status Register 1 SFR

(MIRQSTL, 0xDC) will be set when a transition from negative

to positive reactive power has occurred.

Reactive power no-Load detection

The ADE7169F16 includes a no-load threshold feature on the

reactive energy that eliminates any creep effects in the meter.

The ADE7169F16 accomplishes this by not accumulating

reactive energy if the multiplier output is below the no-load

threshold. When the reactive power is below the no-load

threshold, the RNOLOAD flag in the Interrupt Status Register 1

SFR (MIRQSTL, 0xDC) is set. If the RNOLOAD bit is set in the

Interrupt Enable Register 1 SFR (MIRQENL, 0xD9), the 8052

core has a pending ADE interrupt. The ADE interrupt stays

active until the RNOLOAD status bit is cleared—see Energy

measurement interrupts section.

The No-load threshold level is selectable by setting bits

RNOLOAD in the NLMODE register (0x0E). Setting these bits

to 0b00 disable the no-load detection and setting them to 0b01,

0b10 or 0b11 set the no-load detection threshold to 0.015%,

0.0075% and 0.0037% of the full-scale output frequency of the

multiplier respectively.

VARGAIN[11:0]

VARDIV[7:0]

LPF2

CURRENT

CHANNEL

VOLTAGE

CHANNEL

TIME (nT)

CLKIN

REACTIVE POWER

SIGNAL

VARHR[23:0]

OUTPUTS FROM THE LPF2 ARE

ACCUMULATED (INTEGRATED) IN

THE INTERNAL REACTIVE ENERGY REGISTER

UPPER 24 BITS ARE

ACCESSIBLE THROUGH

VARHR[23:0] REGISTER

WAVEFORM

VALUES

VAROS[15:0]

sgn

2-6 2-7 2-8

FOR WAVEF0RM

SAMPLING

HPF

90° PHASE

SHIFTING FILTER

PHCAL[7:0]

DIGITAL TO FREQUENCY

CONVERTER

Figure 45. ADE7169F16 Reactive Energy Calculation

Reactive Energy Calculation

As for active energy, the ADE7169F16 achieves the integration

of the reactive power signal by continuously accumulating the

reactive power signal in an internal non-readable 49-bit energy

the upper 24 bits of this internal register.

The discrete time sample period (T) for the accumulation

calculating the energy, this integration removes any sinusoidal

components that might be in the active power signal. Figure 45

shows this discrete time integration or accumulation. The

reactive power signal in the waveform register is continuously

added to the internal reactive energy register.

The reactive Energy accumulation depends on the setting of the

SAVARM and ABSVARM bits in the ACCMODE register

(0x0F). When both bits are cleared, the addition is signed and

therefore negative energy is subtracted from the reactive energy

contents. When both bits are set, the ADE7169F16 is set to be

in the more restrictive mode, the Absolute Accumulation mode.

When SAVARM bit in the ACCMODE register (0x0F) is set,

the reactive power is accumulated depending on the sign of the

active power. When active power is positive, the reactive power

is added as it is to the reactive energy register. When active

power is negative, the reactive power is subtracted to the

reactive energy accumulator – see VAR anti-tamper

accumulation mode.

When ABSVARM bit in the ACCMODE register (0x0F) is set,

the absolute reactive power is used for the reactive energy

accumulation—see the VAR absolute accumulation mode

section.

The output of the multiplier is divided by VARDIV. If the value

in the VARDIV register is equal to 0, then the internal reactive

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