ADE7169F16 datasheet(88/140 Pages) AD

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Preliminary Technical Data

ADE7169F16

Rev. PrD | Page 88 of 140

LCD DRIVER

The LCD module is capable of directly driving an LCD panel of

24 x 4 segments without compromising any ADE7169F16

functionalities. Using shared pins, the driver can accommodate

an LCD with up to 26 x 4 segments. It is capable of driving

LCDs with 2x, 3x and 4x multiplexing. LCD waveform voltages

generated through internal charge pump circuitry support up to

5V LCDs. An external resistor ladder for LCD waveform

voltage generation is also supported.

The ADE7169F16 has an embedded LCD control circuit, LCD

driver and power supply circuit. The LCD module is functional

in all Operating modes.

LCD SFR REGISTER LIST

There are six LCD control registers that configure the driver for

the specific type of LCD in the end system and set up the user

display preferences. The LCD Configuration SFR (LCDCON,

0x95), LCD Configuration X SFR (LCDCONX, 0x9C) and LCD

Configuration Y SFR (LCDCONY, 0xB1) SFRs contains general

LCD driver configuration information including the LCD

enable and reset, as well as method of LCD voltage generation

and the multiplex level. The LCD Clock SFR (LCDCLK, 0x96)

configures timing settings for LCD frame rate and blink rate.

LCD pins are configured for LCD functionality in the LCD

Segment Enable SFR (LCDSEGE, 0x97) and LCD Segment

Enable 2 SFR (LCDSEGE2, 0xED).

Table 70. LCD Driver SFRs

SFR

address

(hex)

R/W

Name

Description

0x95

R/W

LCDCON

LCD Configuration SFR

0x96

R/W

LCDCLK

LCD Clock

0x97

R/W

LCDSEGE

LCD Segment Enable

0x9C

R/W

LCDCONX

LCD Configuration X

0xAC

R/W

LCDPTR

LCD Pointer

0xAE

R/W

LCDDAT

LCD Data

0xB1

R/W

LCDCONY

LCD Configuration Y

0xED

R/W

LCDSEGE2

LCD Segment Enable 2

Table 71. LCD Configuration SFR (LCDCON, 0x95)

Bit

Location

Bit

Mnemonic

Default

Value

Description

LCDEN

LCD enable.

If this bit is set, the LCD driver is enabled.

LCDRST

LCD data registers are reset to zero.

If this bit is set, the LCD data registers will be reset to zero.

BLINKEN

Blink Mode enable bit.

If this bit is set, blink mode is enabled. The blink mode is configured by the

BLKMOD[1:0] and BLKFREQ[1:0] bits in the LCD Clock SFR (LCDCLK, 0x96)

Force LCD off when in PSM2 (Sleep mode).

The LCD is disabled or enabled in PSM2 by LCDEN bit.

LCDPSM2

The LCD is disabled in PSM2 regarless of LCDEN setting.

LCD clock selection

fLCDCLK

2048Hz

CLKSEL

128Hz

Bias Mode

1/2

BIAS

1/3

1-0

LMUX[1:0]

LCD Multiplex level

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