ADE7169F16 datasheet(87/140 Pages) AD

87 / 140 page

Preliminary Technical Data

ADE7169F16

Rev. PrD | Page 87 of 140

Figure 62: Interrupt System Functional Block Diagram

INTERRUPT VECTORS

When an interrupt occurs, the program counter is pushed onto

the stack, and the corresponding interrupt vector address is

loaded into the program counter. When the interrupt service

routine has been completed, the program counter is popped off

the stack by a RETI instruction. This allows program execution

to resume from where it was interrupted. The interrupt vector

addresses are shown in Table 69.

Table 69. Interrupt Vector Addresses

Source

Vector Address

IE0

0x0003

TF0

0x000B

IE1

0x0013

TF1

0x001B

RI + TI

0x0023

TF2 + EXF2

0x002B

ITEMP (Temperature ADC)

0x0033

ISPI/I2CI

0x003B

IPSM (Power Supply)

0x0043

IADE (Energy Measurement DSP)

0x004B

IRTC (RTC Interval Timer)

0x0053

WDT (Watchdog Timer)

0x005B

WATCH DOG FUNCTIONALITY

The watchdog timer generates a device reset or interrupt within a

reasonable amount of time if the ADE7169F16 enters an

erroneous state, possibly due to a programming error or

electrical noise. The watchdog is enabled by default with a time

out of 2 seconds and will create a system reset if not cleared

within 2 seconds. The watchdog function can be disabled by

clearing the WDE (watchdog enable) bit in the watchdog

control (WatchDog Timer SFR (WDCON, 0xC0). When

enabled, the watchdog circuit generates a system reset or

interrupt (WDS) if the user program fails to set the WDE bit

within a predetermined amount of time (see the PRE3…0 bits in

Table 65). The watchdog timer is clocked from the 32 kHz

external crystal connected between the CLKIN and CLKOUT

pins. The WDCON SFR can be written only by user software if

the double write sequence described in WDWR is initiated on

every write access to the WDCON SFR

Watchdog Timer Interrupt

If the watchdog timer is not cleared within the watchdog

timeout period, a system reset will occur unless the watchdog

timer interrupt is enabled. The watchdog timer interrupt enable

bit is located in the WatchDog Timer SFR (WDCON, 0xC0).

Enabling the watchdog timer interrupt allows the program to

examine the stack or other variables that could have led the

program astray. The watchdog timer interrupt also allows the

watchdog to be used as a long interval timer.

Note that the Watchdog Timer Interrupt is automatically

configured as a high priority interrupt. This interrupt cannot be

disabled by the EA bit in the IE register. Even if all of the other

interrupts are disabled, the watchdog is kept active to watch

over the program. Interrupt Latency

The 8051 architecture requires that at least one instruction

executes between interrupts. To ensure this, the 8051 MCU core

hardware prevents the program counter from jumping to an ISR

immediately after completing a RETI instruction or an access of

the IP and IE registers.

The shortest interrupt latency is 3.25 instruction cycles, 800ns

with a clock of 4.096MHz. The longest interrupt latency for a

high priority interrupt results when a pending interrupt is

generated during a low priority interrupt RETI, followed by a

multiply instruction. This results in a maximum interrupt

latency of 16.25 instruction cycles, 4us with a clock of

4.096MHz.

CONTEXT SAVING

When the 8052 vectors to an interrupt, only the program

counter is saved on the stack. Therefore the interrupt service

routine must be written to ensure that registers that are used in

the main program are restored to their pre-interrupt state.

Common registers that may be modified in the ISR are the

accumulator, and the PSW register. Any general purpose

registers that are used as scratchpads in the ISR should also be

restored before exiting the interrupt. The example 8051 code

shown below shows how to restore some commonly used

registers:

GeneralISR:

; save the current Accumulator value

PUSH

ACC

; save the current status and register bank selection

PUSH

PSW

; service interrupt

…

; restore the status and register bank selection

POP

PSW

; restore the accumulator

POP

ACC

RETI

ADE7169F16 数据表(PDF) 87 Page - Analog Devices

ADE7169F16 数据表(HTML) 87 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载