NXP Semiconductors

17

33982

FUNCTIONAL DESCRIPTION

Functional description

Introduction

The 33982 is a self-protected silicon 2.0 m

 high-side switch used to replace electromechanical relays, fuses, and discrete devices in

power management applications. The 33982 is designed for harsh environments, including self-recovery features. The device is suitable

for loads with high inrush current, as well as motors and all types of resistive and inductive loads.

Programming, control, and diagnostics are implemented via the Serial Peripheral Interface (SPI). A dedicated parallel input is available

for alternate and pulse width modulation (PWM) control of the output. SPI programmable fault trip thresholds allow the device to be

adjusted for optimal performance in the application.

The 33982 is packaged in a power-enhanced 12 mm x 12 mm non-leaded PQFN package with exposed tabs.

Functional pin description

OUTPUT CURRENT MONITORING (CSNS)

The CSNS pin outputs a current proportional to the high-side output current and used externally to generate a ground-referenced voltage

for the microcontroller to monitor output current.

WAKE (WAKE)

This pin is used to input a logic [1] signal in order to enable the watchdog timer function. An internal clamp protects this pin from high

damaging voltages when the output is current limited with an external resistor. This input has a passive internal pull-down.

RESET (RST)

This input pin is used to initialize the device configuration and fault registers, as well as place the device in a low-current sleep mode. The

pin also starts the watchdog timer when transitioning from logic LOW to logic HIGH. This pin should not be allowed to be logic High until

VDD is in regulation. This pin has a passive internal pull-down.

DIRECT IN (IN)

The Input pin is used to directly control the output. This input has an active internal pull-down current source and requires CMOS logic

levels. This input may be configured via the SPI.

FAULT STATUS (FS)

This is an open drain configured output requiring an external pull-up resistor to VDD for fault reporting. When a device fault condition is

detected, this pin is active LOW. Specific device diagnostic faults are reported via the SPI SO pin.

FAIL-SAFE INPUT (FSI)

The value of the resistance connected between this pin and ground determines the state of the output after a watchdog timeout occurs.

Depending on the resistance value, either the output is OFF or ON. When the FSI pin is connected to GND, the watchdog circuit and Fail-

safe operation are disabled. This pin incorporates an active internal pull-up current source.

CHIP SELECT (CS)

This input pin is connected to a chip select output of a master microcontroller (MCU). The MCU determines which device is addressed

(selected) to receive data by pulling the CS pin of the selected device logic Low, enabling SPI communication with the device. Other

unselected devices on the serial link having their CS pins pulled up logic High disregard the SPI communication data sent. This pin

incorporates an active internal pull-up current source.

SERIAL CLOCK (SCLK)

This input pin is connected to the MCU providing the required bit shift clock for SPI communication. It transitions one time per bit

transferred at an operating frequency, fSPI, defined by the communication interface. The 50 percent duty cycle CMOS-level serial clock

signal is idle between command transfers. The signal is used to shift data into and out of the device. This input has an active internal pull-

down current source.

SERIAL INTERFACE (SI)

This is a command data input pin connected to the SPI Serial Data Output of the MCU or to the SO pin of the previous device in a daisy

chain of devices. The input requires CMOS logic level signals and incorporates an active internal pull-down current source. Device control

is facilitated by the input's receiving the MSB first of a serial 8-bit control command. The MCU ensures data is available upon the falling

edge of SCLK. The logic state of SI present upon the rising edge of SCLK loads that bit command into the internal command shift register.