22

NXP Semiconductors

33982

FUNCTIONAL DEVICE OPERATION

If the load current level ever reaches the selected overcurrent low detection level and the overcurrent condition exceeds the programmed

overcurrent time period (tOCx), the device latches the output OFF.

If at any time the current reaches the selected IOCH level, then the device immediately latches the fault and turn OFF the output, regardless

of the selected tOCL driver. For both cases, the device output stays off indefinitely until the device is commanded OFF and then ON again.

REVERSE BATTERY

The output survives the application of reverse voltage as low as -16 V. Under these conditions, the output’s gate is enhanced to keep the

junction temperature less than 150 °C. The ON resistance of the output is fairly similar to that in the Normal mode. No additional passive

components are required.

GROUND DISCONNECT PROTECTION

In the event the 33982 ground is disconnected from load ground, the device protects itself and safely turns OFF the output regardless the

state of the output at the time of disconnection. A 10 k

 resistor needs to be added between the WAKE pin and the rest of the circuitry in

order to ensure that the device turns off in case of a ground disconnect and to prevent this pin to exceed its maximum ratings.

Table 8. Device behavior in case of undervoltage

High-side

Switch (VPWR

Battery

Voltage)



State

UV Enable

IN = 0

(Falling VPWR)

UV Enable

IN = 0

(Rising VPWR)

UV Enable

IN

 = 1

(Falling VPWR)

UV Enable

IN

 = 1

(Rising VPWR)

UV Disable

IN = 0

(Falling or Rising

VPWR)

UV Disable

IN

 = 1

(Falling or Rising

VPWR)

VPWR >

VPWRUV

Output State

OFF

OFF

ON

OFF

OFF

ON

FS State

1

1

1

0

1

1

SPI Fault

Register UVF Bit

0

1 until next read

0

1

0

0

VPWRUV >

VPWR > UVPOR

Output State

OFF

OFF

OFF

OFF

OFF

ON

FS State

0

0

0

0

1

1

SPI Fault

Register UVF Bit

1

1

1

1

0

0

UVPOR > VPWR

> 2.5 V



Output State

OFF

OFF

OFF

OFF

OFF

ON

FS State

1

1

1

1

1

1

SPI Fault

Register UVF Bit 1 until next read

1

1 until next read

1 until next read

0

0

2.5 V > VPWR >

0V

Output State

OFF

OFF

OFF

OFF

OFF

OFF

FS State

1

1

1

1

1

1

SPI Fault

Register UVF Bit 1 until next read

1 until next read

1 until next read

1 until next read

0

0

Comments

UV fault is not

latched

UV fault is not

latched

UV fault is latched

 Typical value; not guaranteed

 While VDD remains within specified range.

= IN is equivalent to IN direct input or IN_spi SPI input.