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NXP Semiconductors

33982

FUNCTIONAL DEVICE OPERATION

Address x100—Direct Input Control Register (DICR)

The DICR register is used by the MCU to enable, disable, or configure the direct IN pin control of the output. A logic [0] on bit D1 enables

the output for direct control by the IN pin. A logic [1] on bit D1 disables the output from direct control. While addressing this register, if the

input was enabled for direct control, a logic [1] for the D0 bit results in a Boolean AND of the IN pin with its corresponding D0 message bit

when addressing the OCR register. Similarly, a logic [0] on the D0 pin results in a Boolean OR of the IN pin with the corresponding

message bits when addressing the OCR register.

The DICR register is useful if there is a need to independently turn on and off several loads that are PWMed at the same frequency and

duty cycle with only one PWM signal. This type of operation can be accomplished by connecting the pertinent direct IN pins of several

devices to a PWM output port from the MCU, and configuring each of the outputs to be controlled via their respective direct IN pin. The

DICR is then used to Boolean AND the direct IN(s) of each of the outputs with the dedicated SPI bit that also controls the output. Each

configured SPI bit can now be used to enable and disable the common PWM signal from controlling its assigned output.

A logic [1] on bit D2 is used to select the high ratio (CSR1, 1/40000) on the CSNS pin. The default value [0] is used to select the low ratio

(CSR0, 1/5400). A logic [1] on bit D3 is used to select the high-speed slew rate. The default value [0] corresponds to the low-speed slew

rate.

Address 0101—Output Switching Delay Register (OSDR)

The OSDR register is used to configure the device with a programmable time delay that is active during Output On transitions that are

initiated via the SPI (not via direct input). Whenever the input is commanded to transition from logic [0] to logic [1], the output are held OFF

for the time delay configured in the OSDR register.

The programming of the contents of this register has no effect on device Fail-safe mode operation. The default value of the OSDR register

is 000, equating to no delay, since the switching delay time is 0 ms. This feature allows the user a way to minimize inrush currents, or

surges, thereby allowing loads to be synchronously switched ON with a single command. Table 14 shows the eight selectable output

switching delay times, which range from 0 ms to 525 ms.

Address 1101—Watchdog Register (WDR)

The WDR register is used by the MCU to configure the watchdog timeout. Watchdog timeout is configured using bits D1 and D0

(Table 15). When bits D1 and D0 are programmed for the desired watchdog timeout period, the WD bit (D7) should be toggled as well to

ensure that the new timeout period is programmed at the beginning of a new count sequence.

Address 0110—No Action Register (NAR)

The NAR register can be used to no-operation fill SPI data packets in a daisy chain SPI configuration. This allows devices to not be

affected by commands being clocked over a daisy-chained SPI configuration, and by toggling the WD bit (D7) the watchdog circuitry

continues to be reset while no programming or data readback functions are being requested from the device.

Table 14. Switching delay

OSD[2:0] (D2:D0)

Turn ON Delay (ms)

000

0

001

75

010

150

011

225

100

300

101

375

110

450

111

525

Table 15. Watchdog timeout

WD[1:0] (D1:D0)

Timing (ms)

00

620

01

310

10

2500

11

1250