NXP Semiconductors

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33982

FUNCTIONAL DEVICE OPERATION

Address 1110—Undervoltage/Overvoltage Register (UOVR)

The UOVR register can be used to disable or enable the overvoltage and/or undervoltage protection. By default ([0]), both protections are

active. When disabled, an undervoltage or overvoltage condition fault is not reported in bits D1 and D0 of the output fault register.

Address x111—TEST

The TEST register is reserved for test and is not accessible with SPI during normal operation.

SERIAL OUTPUT COMMUNICATION (DEVICE STATUS RETURN DATA)

When the CS pin is pulled low, the output status register is loaded. Meanwhile, the data is clocked out MSB- (OD7-) first as the new

message data is clocked into the SI pin. The first eight bits of data clocking out of the SO, and following a CS transition, are dependant

upon the previously written SPI word.

Any bits clocked out of the SO pin after the first eight are representative of the initial message bits clocked into the SI pin since the CS pin

first transitioned to a logic [0]. This feature is useful for daisy chaining devices as well as message verification.

A valid message length is determined following a CS transition of logic [0] to logic [1]. If there is a valid message length, the data is latched

into the appropriate registers. A valid message length is a multiple of eight bits. At this time, the SO pin is tri-stated and the fault status

register is now able to accept new fault status information.

The output status register correctly reflects the status of the STATR-selected register data at the time the CS is pulled to a logic [0] during

SPI communication and/or for the period of time since the last valid SPI communication, with the following exceptions:

• The previous SPI communication was determined to be invalid. In this case, the status reports as though the invalid SPI

communication never occurred.

• Battery transients below 6.0 V resulting in an undervoltage shutdown of the outputs may result in incorrect data loaded into the status

register. The SO data transmitted to the MCU during the first SPI communication following an undervoltage VPWR condition should

be ignored.

•The RST pin transition from a logic [0] to logic [1] while the WAKE pin is at logic [0] may result in incorrect data loaded into the status

register. The SO data transmitted to the MCU during the first SPI communication following this condition should be ignored.

SERIAL OUTPUT BIT ASSIGNMENT

The eight bits of serial output data depend on the previous serial input message, as explained in the following paragraphs. Table 16

summarizes the SO register content.

Bit OD7 reflects the state of the watchdog bit (D7) addressed during the prior communication. The contents of bits OD6:OD0 depend upon

the bits D2:D0 from the most recent STATR command SOA2:SOA0.

Previous Address SOA[2:0]=000

If the previous three MSBs are 000, bits OD6:OD0 reflect the current state of the Fault register (FLTR) (Table 17).

Table 16. Serial output bit map descriptions

Previous STATR

D7, D2, D1, D0

Serial Output Returned Data

SOA3

SOA2

SOA1

SOA0

OD7

OD6

OD5

OD4

OD3

OD2

OD1

OD0

x

0

0

0

WDin

OTF

OCHF

OCLF

OLF

UVF

OVF

FAULT

x

0

0

1

WDin

0

0

1

0

0

CSNS EN

IN_SPI

x

0

1

0

WDin

0

1

0

SOCH

SOCL2

SOCL1

SOCL0

x

0

1

1

WDin

0

1

1

OL_dis

CD_dis

OCLT1

OCLT0

x

1

0

0

WDin

1

0

0

Fast SR

CSNS High

IN dis

A/O

0

1

0

1

0

1

0

1

FSM_HS

OSD2

OSD1

OSD0

1

1

0

1

1

1

0

1

0

WDTO

WD1

WD0

0

1

1

0

0

1

1

0

0

IN Pin

FSI Pin

WAKE Pin

1

1

1

0

1

1

1

0

0

1110

UV_dis

OV_dis

x

1

1

1

WDin

–

–

–

See Table 2

–

–

–

x = Don’t care.