TMS320C6421 datasheet(30/59 Pages) TI

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TMS320C6421

Fixed-Point Digital Signal Processor

SPRS346A – JANUARY 2007 – REVISED MARCH 2007

Table 2-14. DDR2 Memory Controller Terminal Functions (continued)

SIGNAL

TYPE(1)

OTHER(2)(3)

DESCRIPTION

ZWT

ZDU

NAME

NO.

DDR_D[15]

AB6

DDR_D[14]

DDR_D[13]

AA6

DDR_D[12]

AB5

DDR_D[11]

DDR_D[10]

AA5

DDR_D[9]

DDR_D[8]

AB4

I/O/Z

DVDDR2

DDR2 bi-directional data bus is configured as 16-bits wide.

DDR_D[7]

DDR_D[6]

AB3

DDR_D[5]

DDR_D[4]

AA3

DDR_D[3]

AA2

DDR_D[2]

DDR_D[1]

DDR_D[0]

DDR_VREF

T15

W18

(3)

Reference voltage input for the SSTL_18 I/O buffers

DDR_VSSDLL

T13

W15

GND

(3)

Ground for the DDR2 DLL

DDR_VDDDLL

T12

W14

(3)

Power (1.8 Volts) for the DDR2 Digital Locked Loop

Impedance control for DDR2 outputs. This must be connected via a

DDR_ZN

T10

W12

(3)

200-

Ω resistor to DV

DDR2.

Impedance control for DDR2 outputs. This must be connected via a

DDR_ZP

T11

W13

(3)

200-

Ω resistor to V

SS.

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