TMS320C6421 datasheet(25/59 Pages) TI

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TMS320C6421

Fixed-Point Digital Signal Processor

SPRS346A – JANUARY 2007 – REVISED MARCH 2007

Table 2-12. EMIFA Terminal Functions (EMIFA Pinout Mode 2, AEM[2:0] = 010) (continued)

SIGNAL

TYPE(1)

OTHER(2)(3)

DESCRIPTION

ZWT

ZDU

NAME

NO.

This pin is multiplexed between EMIFA and GPIO.

EM_A[4]/

IPD

A17

B21

I/O/Z

GP[10]/(PLLMS2)

DVDD33

For EMIFA (AEM[2:0] = 010), this pin is address bit 4 output EM_A[4].

This pin is multiplexed between EMIFA and GPIO.

EM_A[3]/

IPD

B18

D21

I/O/Z

GP[11]

DVDD33

For EMIFA (AEM[2:0] = 010), this pin is address bit 3 output EM_A[3].

This pin is multiplexed between EMIFA and GPIO.

EM_A[2]/(CLE)/

IPD

B16

A20

I/O/Z

GP[8]/(PLLMS0)

DVDD33

For EMIFA (AEM[2:0] = 010), this pin is address bit 2 output EM_A[2].

This pin is multiplexed between EMIFA and GPIO.

EM_A[1]/(ALE)/

IPD

A16

B20

I/O/Z

GP[9]/(PLLMS1)

DVDD33

For EMIFA (AEM[2:0] = 010), this pin is address output EM_A[1].

This pin is multiplexed between EMIFA and GPIO.

For EMIFA (AEM[2:0] = 010), this pin is Address output EM_A[0],

EM_A[0]/

IPD

B17

C21

I/O/Z

which is the least significant bit on a 32-bit word address.

GP[7]/(AEM2)

DVDD33

For an 8-bit asynchronous memory, this pin is the 3rd bit of the

address.

EM_D0/

IPD

D16

E21

I/O/Z

GP[14]

DVDD33

EM_D1/

IPD

D18

G20

I/O/Z

GP[15]

DVDD33

EM_D2/

IPD

D17

E22

I/O/Z

GP[16]

DVDD33

EM_D3/

IPD

These pins are multiplexed between EMIFA and GPIO.

E16

F20

I/O/Z

GP[17]

DVDD33

For EMIFA (AEM[2:0] = 010), these pins are the 8-bit bi-directional

EM_D4/

IPD

E18

G21

I/O/Z

data bus (EM_D[7:0]).

GP[18]

DVDD33

EM_D5/

IPD

E17

F22

I/O/Z

GP[19]

DVDD33

EM_D6/

IPD

F16

F21

I/O/Z

GP[20]

DVDD33

EM_D7/

IPD

F17

H20

I/O/Z

GP[21]

DVDD33

EMIFA FUNCTIONAL PINS: 8-Bit NAND (EMIFA Pinout Mode 2, AEM[2:0] = 010)

This pin is multiplexed between EMIFA (NAND) and GPIO.

EM_A[1]/(ALE)/

IPD

A16

B20

I/O/Z

When used for EMIFA (NAND) , this pin is the Address Latch Enable

GP[9]/(PLLMS1)

DVDD33

output (ALE).

This pin is multiplexed between EMIFA (NAND) and GPIO.

EM_A[2]/(CLE)/

IPD

B16

A20

I/O/Z

When used for EMIFA (NAND) , this pin is the Command Latch

GP[8]/(PLLMS0)

DVDD33

Enable output (CLE).

EM_WAIT/

IPU

E15

D20

I/O/Z

When used for EMIFA (NAND), it is ready/busy input (RDY/BSY).

(RDY/BSY)

DVDD33

IPU

EM_OE

D15

D19

I/O/Z

When used for EMIFA (NAND), this pin is read enable output (RE).

DVDD33

IPU

EM_WE

E14

C19

I/O/Z

When used for EMIFA (NAND), this pin is write enable output (WE).

DVDD33

This pin is multiplexed between EMIFA (NAND) and GPIO.

For EMIFA (NAND), this pin is Chip Select 2 output EM_CS2 for use

with NAND flash.

EM_CS2/

IPD

This is the chip select for the default boot and ROM boot modes.

C19

C22

I/O/Z

GP[12]

DVDD33

Note: This pin features an internal pulldown (IPD). If this pin is

connected and used as an EMIFA chip select signal, for proper device

operation, an external pullup resistor must be used to ensure the

EM_CSx function defaults to an inactive (high) state.

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