TMS320C6421 datasheet(24/59 Pages) TI

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TMS320C6421

Fixed-Point Digital Signal Processor

SPRS346A – JANUARY 2007 – REVISED MARCH 2007

Table 2-12. EMIFA Terminal Functions (EMIFA Pinout Mode 2, AEM[2:0] = 010) (continued)

SIGNAL

TYPE(1)

OTHER(2)(3)

DESCRIPTION

ZWT

ZDU

NAME

NO.

This pin is multiplexed between EMIFA and GPIO.

IPD

EM_A[21]/GP[34]

D12

C16

I/O/Z

For EMIFA (AEM[2:0] = 010), this pin is address bit 21 output

DVDD33

EM_A[21].

This pin is multiplexed between EMIFA and GPIO.

IPD

EM_A[20]/GP[44]

C12

C15

I/O/Z

For EMIFA (AEM[2:0] = 010), this pin is address bit 20 output

DVDD33

EM_A[20].

This pin is multiplexed between EMIFA and GPIO.

IPD

EM_A[19]/GP[45]

B12

C14

I/O/Z

For EMIFA (AEM[2:0] = 010), this pin is address bit 19 output

DVDD33

EM_A[19].

This pin is multiplexed between EMIFA and GPIO.

IPD

EM_A[18]/GP[46]

D11

A14

I/O/Z

For EMIFA (AEM[2:0] = 010), this pin is address bit 18 output

DVDD33

EM_A[18].

This pin is multiplexed between EMIFA and GPIO.

IPD

EM_A[17]/GP[47]

A11

B14

I/O/Z

For EMIFA (AEM[2:0] = 010), this pin is address bit 17 output

DVDD33

EM_A[17].

This pin is multiplexed between EMIFA and GPIO.

IPD

EM_A[16]/GP[48]

C11

B13

I/O/Z

For EMIFA (AEM[2:0] = 010), this pin is address bit 16 output

DVDD33

EM_A[16].

This pin is multiplexed between EMIFA and GPIO.

IPD

EM_A[15]/GP[49]

B11

C13

I/O/Z

For EMIFA (AEM[2:0] = 010), this pin is address bit 15 output

DVDD33

EM_A[15].

This pin is multiplexed between EMIFA and GPIO.

IPD

EM_A[14]/GP[50]

A10

A13

I/O/Z

For EMIFA (AEM[2:0] = 010), this pin is address bit 14 output

DVDD33

EM_A[14].

This pin is multiplexed between EMIFA and GPIO.

IPD

EM_A[13]/GP[51]

B10

A12

I/O/Z

For EMIFA (AEM[2:0] = 010), this pin is address bit 13 output

DVDD33

EM_A[13].

This pin is multiplexed between EMIFA and GPIO.

IPD

EM_A[12]/GP[89]

D10

B12

I/O/Z

For EMIFA (AEM[2:0] = 010), this pin is address bit 12 output

DVDD33

EM_A[12].

This pin is multiplexed between EMIFA and GPIO.

IPD

EM_A[11]/GP[90]

C10

C12

I/O/Z

For EMIFA (AEM[2:0] = 010), this pin is address bit 11 output

DVDD33

EM_A[11].

This pin is multiplexed between EMIFA and GPIO.

IPD

EM_A[10]/GP[91]

B11

I/O/Z

For EMIFA (AEM[2:0] = 010), this pin is address bit 10 output

DVDD33

EM_A[10].

This pin is multiplexed between EMIFA and GPIO.

IPD

EM_A[9]/GP[92]

C11

I/O/Z

DVDD33

For EMIFA (AEM[2:0] = 010), this pin is address bit 9 output EM_A[9].

This pin is multiplexed between EMIFA and GPIO.

IPD

EM_A[8]/GP[93]

A11

I/O/Z

DVDD33

For EMIFA (AEM[2:0] = 010), this pin is address bit 8 output EM_A[8].

This pin is multiplexed between EMIFA and GPIO.

IPD

EM_A[7]/GP[94]

C10

I/O/Z

DVDD33

For EMIFA (AEM[2:0] = 010), this pin is address bit 7 output EM_A[7].

This pin is multiplexed between EMIFA and GPIO.

IPD

EM_A[6]/GP[95]

B10

I/O/Z

DVDD33

For EMIFA (AEM[2:0] = 010), this pin is address bit 6 output EM_A[6].

This pin is multiplexed between EMIFA and GPIO.

IPD

EM_A[5]/GP[96]

A10

I/O/Z

DVDD33

For EMIFA (AEM[2:0] = 010), this pin is address bit 5 output EM_A[5].

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