TMS320C6421 datasheet(37/59 Pages) TI

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TMS320C6421

Fixed-Point Digital Signal Processor

SPRS346A – JANUARY 2007 – REVISED MARCH 2007

Table 2-19. Multichannel Buffered Serial Port 0 (McBSP0) Terminal Functions

SIGNAL

TYPE(1)

OTHER(2)(3)

DESCRIPTION

ZWT

ZDU

NAME

NO.

Multichannel Buffered Serial Port 0 (McBSP0)

Pin Muxing Control: TBD

CLKS0/TOUT0L/

IPD

This pin is multiplexed between McBSP0, Timer0, and GPIO.

I/O/Z

GP[97]

DVDD33

For McBSP0, it is McBSP0 external clock source (I).

ACLKR0/CLKX0/

IPD

This pin is multiplexed between McASP0, McBSP0, and GPIO.

I/O/Z

GP[99]

DVDD33

For McBSP0, it is McBSP0 transmit clock CLKX0 (I/O/Z).

AHCLKR0/CLKR0/

IPD

This pin is multiplexed between McASP0, McBSP0, and GPIO.

I/O/Z

GP[101]

DVDD33

For McBSP0, it is McBSP0 receive clock CLKR0 (I/O/Z).

This pin is multiplexed between McASP0, McBSP0, and GPIO.

AXR0[2]/FSX0/

IPD

I/O/Z

For McBSP0, it is McBSP0 transmit frame synchronization FSX0

GP[103]

DVDD33

(I/O/Z).

This pin is multiplexed between McASP0, McBSP0, and GPIO.

AXR0[3]/FSR0/

IPD

I/O/Z

For McBSP0, it is McBSP0 receive frame synchronization FSR0

GP[102]

DVDD33

(I/O/Z).

AXR0[1]/DX0/

IPD

This pin is multiplexed between McASP0, McBSP0, and GPIO.

I/O/Z

GP[104]

DVDD33

For McBSP0, it is McBSP0 data transmit output DX0 (O/Z).

AFSR0/DR0/

IPD

This pin is multiplexed between McASP0, McBSP0, and GPIO.

I/O/Z

GP[100]

DVDD33

For McBSP0, it is McBSP0 data receive input DR0 (I).

(1)

I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal

(2)

IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external

pullup/pulldown resistors are required, see Section 3.2.1, Pullup/Pulldown Resistors.

(3)

Specifies the operating I/O supply voltage for each signal

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