USB97C100QFP datasheet(17/64 Pages) SMSC

17 / 64 page

SMSC DS – USB97C100

Page 17

Rev. 01/03/2001

MCU REGISTER DESCRIPTION

MCU Runtime Registers

Table 9 - Interrupt 0 Source Register

ISR_0

(0x7F00 - RESET=0x00)

INTERRUPT 0 SOURCE REGISTER

BIT

NAME

R/W

DESCRIPTION

IRQ3

External interrupt input.

0 = Inactive

1 = Active

IRQ2

External interrupt input.

0 = Inactive

1 = Active

IRQ1

External interrupt input.

0 = Inactive

1 = Active

IRQ0

External interrupt input.

0 = Inactive

1 = Active

RX_PKT

1 = A Packet Number (PNR) has been successfully queued

on the RXFIFO.

TX_EMPTY

1 = Whenever an enabled TX Endpoint's FIFO becomes

empty. This will occur when the last queued packet in one of

the 16 TX queues is successfully transferred to the Host.

TX_PKT

1 = A Packet was successfully transmitted.

ISADMA

1 = When a selected 8237 channels in

BUS_STAT/BUS_MASK register pair either reached Terminal

Count or have a new DMA Request Pending.

These bits are automatically cleared each time this register is read. Therefore, each time this register is read all

pending interrupts must be serviced before continuing normal operation.

Notes:

TX_EMPTY is useful for warning of USB performance degradation. This interrupt indicates that the next time the

Host polls the affected endpoint, it will receive a NAK for that endpoint, thus reducing effective overall bandwidth

due to retries. Firmware must use TX_STAT A, B, and C to determine which endpoint queue is empty.

When ISADMA causes an interrupt, the 8237 CH_STAT register should also be read and serviced when the bit

causing the interrupt is to be rearmed. When ISR_0 is read and the ISADMA bit is cleared, any other low-to-high

transitions in the BUS_STAT register bits that are not masked will still cause an interrupt.

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