USB97C100QFP datasheet(56/64 Pages) SMSC

56 / 64 page

SMSC DS – USB97C100

Page 56

Rev. 01/03/2001

PARAMETER

SYM

CONDITIONS

(NOTE 1, 2, 3)

MIN

TYP

MAX

UNIT

Differential to EOP

transition Skew

TDEOP

Note 7 and

FIGURE 8

-2

Receiver Data Jitter

Tolerance

To next Transition

For Paired Transitions

TJR1

TJR2

Note 7 and FIGURE 9

-18.5

-9

18.5

9.0

Differential Data Jitter

To next Transition

For Paired Transitions

TXJR1

TXJR2

Note 7 and FIGURE 7

-18.5

-9

18.5

9.0

EOP Width at receiver

Must reject as EOP

Must Accept

TEOPR1

TEOPR2

Note 7 and

FIGURE 8

CABLE IMPEDANCE AND TIMING:

Cable Impedance (Full

Speed)

(45

Ω +/- 15%)

38.75

51.75

Ω

Cable Delay (One Way)

TCBL

FIGURE 6

Note 1: All voltages are measured from the local ground potential, unless otherwise specified.

Note 2: All timing use a capacitive load (CL) to ground of 50pF, unless otherwise specified.

Note 3: Full speed timings have a 1.5K

Ω pull-up to 2.8 V on the D+ data line.

Note 4: Measured from 10% to 90% of the data signals.

Note 5: The rising and falling edges should be smoothly transiting (monotonic).

Note 6: Timing differences between the differential data signals.

Note 7: Measured at crossover point of differential data signals.

Note 8: These are relative to the 24 MHz crystal.

FIGURE 10 - 8051 IO WRITE CYCLE

DATA VALID

AEN

SA[x]

nIOW

SD[x]

USB97C100QFP 数据表(PDF) 56 Page - SMSC Corporation

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