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USB97C100QFP 数据表(PDF) 40 Page - SMSC Corporation |
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USB97C100QFP 数据表(HTML) 40 Page - SMSC Corporation |
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40 / 64 page ![]() SMSC DS – USB97C100 Page 40 Rev. 01/03/2001 MMU Free Pages Register MMU Free Pages bits, and a global NAK_ALLRX (this can only NACK OUT and Bulk packets) control bit for the firmware to view the real time status of the 32 page allocation bits. This allows the MCU to set NAK_ALLRX which would inhibit the SIE from asking the SIEDMA to allocate packets, MCU checks how many pages are left, issue an allocate if enough are free, and then release the SIE/SIEDMA. For the current design, the number of free pages would range from 0x00 to 0x1F (32) pages left unallocated. The indication of pages free may be invalid during an allocation or deallocation. Table 66 - Pages Free In The MMU PAGS_FREE (0x7F56 - RESET=0x20) PAGES FREE IN THE MMU BIT NAME R/W DESCRIPTION 7 NAK_ALLRX R/W NACK All received packets 0 = Normal Operation (Default) 1 = NACK all RX packets 6 Reserved 0 Reserved [5:0] PAGS_FREE R These bits indicate the number of free pages in the MMU. Notes: Firmware can set a NAK_ALLRX bit to inhibit the SIE from asking the SIEDMA to allocate any pages while the MCU is observing the page free bits. This register is used to indicate how many pages are left in many situations, including after an RX_OVRN, before a multi-packet allocation, etc. This eliminates the possibility of a failed allocation, simplifying software without adding additional hardware to abort an allocation. 16 BYTE DEEP TX COMPLETION FIFO REGISTER Table 67 - TX Management Register 2 TX_MGMT (0x7F57 - RESET=0x80) TX Management Register BIT NAME R/W DESCRIPTION 7 CTX_EMTY R Completed TX FIFO empty status 0 = Has one or more TX packet 1 = Empty 6 CTX_FULL R Completed TX FIFO full status 0 = Not FULL 1 = FULL 5 Reserved R Reserved [4:0] CTX_FIFO R This is the data port for the 16 deep TX completion FIFO. This FIFO is automatically updated by hardware with the last successfully completed transmit packet. It is the responsibility of software to ensure that this FIFO never overflows and/or becomes full. |
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