USB97C100QFP datasheet(41/64 Pages) SMSC

41 / 64 page

SMSC DS – USB97C100

Page 41

Rev. 01/03/2001

Table 68 - Receive Packet Number FIFO Register

RXFIFO

(0x7F58)

NEXT RX PACKET NUMBER FIFO REGISTER

BIT

NAME

R/W

DESCRIPTION

RXFIFO_EMPT

1 = No pending packets from the host to be processed

RXFIFO_FULL

1 = The SIEDMA will not accept packets from the host (via RX

Overflow)

Reserved

[4:0]

P[4:0]

Packet Number

When a packet has been received, and the 8-byte header has

been written by the SIEDMA, the associated Packet Number is

placed in this FIFO

A "complete" reception requires that the 8 byte status header is correctly written into the packet buffer, with the

correct data, and moved into the RX Packet Number FIFO. A "successful" reception requires that the CRC and PID

check bits of a

"complete" reception are good. The hardware queues only "complete" packets. Firmware must

determine if "complete" packets were "successful". Corrupted token packets causes the complete data payload to

be ignored.

Tx FIFO POP Register

This register is used to help software manage TX Queues.

This will provide a method to handle a

CLEAR_FEATURE:ENDPOINT_STALL” condition gracefully.

When read, this register will return the Packet

Number of the next packet waiting on the TX queue pointed to by MMUTX_SEL register, AND it will pop that Packet

Number off of the selected TX FIFO.

Table 69 - POP TX FIFO

POP_TX

(0x7F59 – RESET=0x80)

POP TX FIFO

BIT

NAME

R/W

DESCRIPTION

POPTX_STAT

POP TX FIFO empty status

0 = Has one or more TX packet

1 = Empty

[6:5]

Reserved

[4:0]

POP_TX

This 5 bit value is the packet number or handle that is at the top of

the TX FIFO pointer to by MMUTX_SEL. The TX FIFO is popped

when this register is read.

Note: It is the software's responsibility to ensure that the appropriate TX EP is disabled during this operation, and to

issue a deallocate command if desired.

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