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USB97C100QFP 数据表(PDF) 61 Page - SMSC Corporation |
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USB97C100QFP 数据表(HTML) 61 Page - SMSC Corporation |
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61 / 64 page ![]() SMSC DS – USB97C100 Page 61 Rev. 01/03/2001 FIGURE 16 - 8051 FLASH MEMORY READ TIMING Table 94 - 8051 Flash Memory Read Timing Parameters PARAMETER MIN TYP MAX OSCILLATOR EQUATION UNITS t1 SA[19:0] Valid to nMEMRD asserted 107 4t-60 ns t2 nMEMRD active pulse width 150 6t-100 ns t3 nMEMRD deasserted to SA[19:0] Invalid 21.66 t-20 ns t4 nMEMRD asserted to Data Valid 0 ns t7 SD[7:0] data Hold from nMEMRD deasserted 0ns t8 nMEMRD deasserted to SD[7:0] data tri-state 64 2t-20 ns t11 FALE deasserted to nMEMRD asserted 84 165 3t +/- 40 ns Note: Min and Max delays shown for an 8051 clock of 24MHz, to calculate timing delays for other clock frequencies use the Oscillator Equations, where T=1/Fclk. t3 t1 t2 t4 t7 DATA VALID FALE SA[19:0] nMEMRD SD[7:0] t8 t10 t11 |
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