USB97C100QFP datasheet(9/64 Pages) SMSC

9 / 64 page

SMSC DS – USB97C100

Page 9

Rev. 01/03/2001

FUNCTIONAL DESCRIPTION

The USB97C100 incorporates a USB Serial Interface Engine (SIE), 8051 Microcontroller Unit (MCU), Serial Interface

Engine DMA (SIEDMA), a programmable 8237 ISA bus DMA controller (ISADMA), 4K bytes of SRAM for data

stream buffering, and a patented MMU (Memory Management Unit) to dynamically manage buffer allocation. The

semi-automatic nature of the SIEDMA, ISADMA, and MMU blocks frees the MCU to provide enumeration, protocol

and power management. A bus arbiter integrated into the MMU assures that transparent access between the

SIEDMA, ISADMA, and MCU to the SRAM occurs.

Serial Interface Engine (SIE)

The SIE is a USB low-level protocol interpreter.

The SIE controls the USB bus protocol, packet

generation/extraction, parallel-to-serial/serial-to-parallel conversion, CRC coding/decoding, bit stuffing, and NRZI

coding/decoding.

The SIE can be dynamically configured as having any combination of 0-16 transmit, and 0-16 receive endpoints, for

up to 4 independent addresses. There are 3 alternate and one local address. The alternate addresses, for example,

can be used for Hub addresses. The SIE can also "Receive All Addresses" for bus snooping.

Micro Controller Unit (MCU)

The 8051 embedded controller is a static CMOS MCU which is fully software compatible with the industry standard

Intel 80C51 micro-controller. All internal registers of the USB97C100 blocks are mapped into the external memory

space of the MCU.

A detailed description of the microcontroller’s internal registers and instruction set can be found in the “USB97C100

Programmer’s Reference Guide”.

SIEDMA

This is a simplified DMA controller, which automatically transfers data between SIE and SRAM via MMU control. The

SIEDMA appends a status header containing frame number, endpoint, and byte count to each incoming packet

before notifying the MCU of its arrival. This block’s operation is transparent to the firmware.

Memory Management Unit (MMU) Register Description

This patented MMU consists of a 4k buffer RAM which is allocated in 32 pages of 128 bytes. Packets can be

allocated with up to 10 pages each (1280 bytes). The buffer can therefore concurrently hold up to 32 packets with a

64 byte payload. For isochronous pipes, it can hold 3 packets with a 1023 byte payload each, and still have room for

two more 64 byte packets.

This block supports 16 independent transmit FIFO queues (one for each endpoint), and a single receive queue.

Each endpoint can have up to five transmit packets queued. The receive queue can accept 16 packets of any size

combination before forcing the host to back off.

The arbiter makes the single-ported buffer RAM appear to be simultaneously available to the MCU, the four channels

of the ISADMA, and the SIEDMA for receiving and transmitting packets.

ISADMA

This is an industry standard 8237 DMA controller to transfer data between the ISA bus and the SRAM under MMU

control. This DMA contains status and control registers which can be accessed and programmed by the 8051

controller. The 8237 can run at 2, 4, or 8 MHz internally, or via an external clock to synchronize it with another

source.

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