数据搜索系统，热门电子元器件搜索
  Chinese  ▼
ALLDATASHEETCN.COM

X  

预览 PDF HTML

USB97C100QFP 数据表(PDF) 28 Page - SMSC Corporation

部件名 USB97C100QFP
功能描述  Multi-Endpoint USB Peripheral Controller
PDF  64 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  SMSC [SMSC Corporation]
网页  http://www.smsc.com
标志 SMSC - SMSC Corporation

USB97C100QFP 数据表(HTML) 28 Page - SMSC Corporation

Back Button USB97C100QFP Datasheet HTML 24Page - SMSC Corporation USB97C100QFP Datasheet HTML 25Page - SMSC Corporation USB97C100QFP Datasheet HTML 26Page - SMSC Corporation USB97C100QFP Datasheet HTML 27Page - SMSC Corporation USB97C100QFP Datasheet HTML 28Page - SMSC Corporation USB97C100QFP Datasheet HTML 29Page - SMSC Corporation USB97C100QFP Datasheet HTML 30Page - SMSC Corporation USB97C100QFP Datasheet HTML 31Page - SMSC Corporation USB97C100QFP Datasheet HTML 32Page - SMSC Corporation Next Button
Zoom Inzoom in Zoom Outzoom out
 28 / 64 page
background image
SMSC DS – USB97C100
Page 28
Rev. 01/03/2001
Table 34 - ISA Bus Status Register
BUS_STAT
(0x7F73 - RESET=0xXX)
ISA BUS STATUS REGISTER
BIT
NAME
R/W
DESCRIPTION
7
CH3RQ
R
Channel 3 DMA Request
0 = No Request Pending
1 = Request Pending
6
CH2RQ
R
Channel 2 DMA Request
0 = No Request Pending
1 = Request Pending
5
CH1RQ
R
Channel 1 DMA Request
0 = No Request Pending
1 = Request Pending
4
CH0RQ
R
Channel 0 DMA Request
0 = No Request Pending
1 = Request Pending
3
CH3TC
R
Channel 3 Terminal Count Reached
0 = No
1 = Yes
2
CH2TC
R
Channel 2 Terminal Count Reached
0 = No
1 = Yes
1
CH1TC
R
Channel 1 Terminal Count Reached
0 = No
1 = Yes
0
CH0TC
R
Channel 0 Terminal Count Reached
0 = No
1 = Yes
Notes:
Each bit in this register reflects the current value of the corresponding bit in the 8237 CH_STAT status register.
The 8237 clears bits 3..0 in the CH_STAT status register when the 8051 reads it through the ISA Bus I/O
Window.
Reading the BUS_STAT register does not clear or otherwise affect the BUS_STAT register.
The ISADMA bit in ISR_0 is latched high whenever any bit in BUS_STAT that is enabled in BUS_MASK
transitions from low to high.
This register is intended (1) to provide a view into the status of the 8237 without having to assume control of the
ISA bus during DMA transfers, and (2) to provide a means for generating the ISADMA interrupt in ISR_0 which
indicates that a DMA transfer has completed and that the 8051 should take control of the bus and setup the
8237 for its next transfer. Bits 7-4 can be used to generate additional interrupt requests from the DREQ pins, or
simply to monitor channel request status by masking them.



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64


数据表 下载

Go To PDF Page


链接网址



ALLDATASHEET是否为您带来帮助?  [ DONATE ] 

关于 Alldatasheet   |   广告服务   |   联系我们   |   隐私政策   |   数据表链接    |   链接交换   |   制造商名单
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com