USB97C100QFP datasheet(5/64 Pages) SMSC

5 / 64 page

SMSC DS – USB97C100

Page 5

Rev. 01/03/2001

DESCRIPTION OF PIN FUNCTIONS

Table 1 - USB97C100 Pin Configuration

QFP PIN

NUMBER

SYMBOL

PIN DESCRIPTION

BUFFER

TYPE

ISA INTERFACE

100

READY

Channel is ready when high.

ISA memory or slave devices use this signal to lengthen a bus

cycle from the default time. Extending the length of the bus

cycle can only be done when the bus cycles are derived from

the Internal DMA controller core. 8051 MCU generated Memory

or I/O accesses cannot and will not be extended even if

READY is asserted low by an external ISA slave device. The

external slave device negates this signal after decoding a valid

address and sampling the command signals (nIOW, nIOR,

nMEMW, and nMEMR). When the slave’s access has

completed, this signal should be allowed to float high.

104, 106,

108, 110

DRQ[3:0]

DMA Request channels 3-0; active high.

These signals are used to request DMA service from the DMA

controller. The requesting device must hold the request signal

until the DMA controller drives the appropriate DMA

acknowledge signal (nDACK[3:0]).

105, 107,

109, 111

nDACK

[3:0]

DMA Acknowledge channels 3-0; active low.

These signals are used to indicate to the DMA requesting

device that it has been granted the ISA bus.

103

DMA Terminal Count; active high.

This signal is used to indicate that a DMA transfer has

completed.

19-13,

127-7,

9-12

SA[19:0]

System Address Bus

These signals address memory or I/O devices on the ISA bus.

112-115,

117-120

SD[7:0]

System Data Bus

These signals are used to transfer data between system

devices.

I/O8

122

AEN

Address Enable

This signal indicates address validation to I/O devices. When

low this signal indicates that an I/O slave may respond to

addresses and I/O commands on the bus. This signal is high

during DMA cycles to prevent I/O slaves from interpreting DMA

cycles as valid I/O cycles.

123

nIOW

I/O Write; active low.

This signal indicates to the addressed ISA I/O slave to latch

data from the ISA bus.

124

nIOR

I/O Read; active low.

This signal indicates to the addressed ISA I/O slave to drive

data on the ISA bus.

125

nMEMR

Memory read; active low

This signal indicates to the addressed ISA memory slave to

drive data on the ISA bus.

126

nMEMW

Memory write; active low

This signal indicates to the addressed ISA memory slave to

latch data from the ISA bus.

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