USB97C100QFP datasheet(32/64 Pages) SMSC

32 / 64 page

SMSC DS – USB97C100

Page 32

Rev. 01/03/2001

Table 40 - 8237 Address Programming Guide

8237 INTERNAL ADDRESS PROGRAMMING GUIDE

BIT

NAME

DESCRIPTION

INT_EXT

Indicates whether this address refers to Internal Buffer RAM or

External ISA Memory Space

0 = External

1 = Internal

When this bit is set to zero (0), I/O capability is added to External

Memory DMA. This capability can only be used for DMA channels 2

or 3.

[14:10]

PN[4:0]/SA[14:10]

External Address -or- Internal Packet Number

SA[14..10] when INT_EXT=0

PN[4..0] when INT_EXT=1

[9:0]

PTR[9:0]/SA[9:0]

External Address -or- Internal Packet Offset Pointer

SA[9..0] when INT_EXT=0

PTR[9..0] when INT_EXT=1

Note:

SA[19..15] are driven low when the 8237 is accessing external ISA memory. PTR10 is driven low when the

8237 is accessing internal buffer RAM. Note that the actual transfer size for the ISADMA is limited to 1024

bytes, which limits the payload data to 1016 bytes per transfer when the 8 byte header is skipped. Also note

that the 8051 still has access to 1Meg of external RAM through the MEMBASE register and it is

independent of the 8237's 32k external limit.

Table 41 - Channel 0 Current Address Register

CH0_ADDR

(ISA 0x0000)

CHANNEL 0 CURRENT ADDRESS

BIT

NAME

R/W

DESCRIPTION

[7:0]

CH0_ADDRL

R/W

Lower 8 bits of Base and Current Address when Byte F/F = 0

[7:0]

CH0_ADDRH

R/W

Upper 8 bits of Base and Current Address when Byte F/F = 1

Note:

Byte F/F is an internal Flip Flop which reflects which byte (high or low) is being written. The CLEAR_FF

written. See the Address Programming Table for 16 bit Address definitions.

Table 42 - Channel 0 Byte Count Register

CH0_CNT

(ISA 0x0001)

CHANNEL 0 BYTE COUNT

BIT

NAME

R/W

DESCRIPTION

[7:0]

CH0_CNTL

R/W

Lower 8 bits of Byte Count when Byte F/F = 0

[7:0]

CH0_CNTH

R/W

Upper 8 bits of Byte Count when Byte F/F = 1

Note:

The CLEAR_FF register should be written to before writing this register to guarantee which byte (high or

low) is being written. See Address Programming Table for 16 bit Address definitions.

Table 43 - Channel 1 Current Address Register

CH1_ADDR

(ISA 0x0002)

CHANNEL 1 CURRENT ADDRESS

BIT

NAME

R/W

DESCRIPTION

[7:0]

CH1_ADDRL

R/W

Lower 8 bits of Base and Current Address when Byte F/F = 0

[7:0]

CH1_ADDRH

R/W

Upper 8 bits of Base and Current Address when Byte F/F = 1

Note:

The CLEAR_FF register should be written to before writing this register to guarantee which byte (high or

low) is being written. See the Address Programming Table for 16 bit Address definitions.

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