SC28C94 datasheet(8/38 Pages) PHILIPS

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Philips Semiconductors

Product specification

SC28C94

Quad universal asynchronous receiver/transmitter (QUART)

1998 Aug 19

Timer Mode

In the timer mode a symmetrical square wave is generated whose

half period is equal in time to division of the selected counter/timer

clock frequency by the 16-bit number loaded in the CTLR CTUR.

Thus, the frequency of the counter/timer output will be equal to the

counter/timer clock frequency divided by twice the value of the

CTUR CTLR. While in the timer mode the ISR bit 3 (ISR[3]) will be

set each time the counter/timer transitions from 1 to 0. (High to low)

This continues regardless of issuance of the stop counter command.

ISR[3] is reset by the stop counter command. NOTE: Reading of

the CTU and CTL registers in the timer mode is not meaningful.

When the C/T is used to generate a baud rate

and the C/T is

selected through the CSR then the receivers and/or transmitter will

be operating in the 16x mode. Calculation for the number ‘n’ to

program the counter timer upper and lower registers is shown below.

n=2 x 16 x Baud rate desired/(C/T Clock Frequency

Often this division will result in a non-integer number; 26.3 for

example. One can only program integer numbers to a digital divider.

Therefore 26 would be chosen. This gives a baud rate error of

0.3/26.3 which is 1.14%; well within the ability of the asynchronous

mode of operation.

Counter Mode

In the counter mode the counter/timer counts the value of the CTLR

CTUR down to zero and then sets the ISR[3] bit and sets the

counter/timer output from 1 to 0. It then rolls over to 65,365 and

continues counting with no further observable effect.

Reading the C/T in the counter mode outputs the present state of

the C/T. If the C/T is not stopped, a read of the C/T may result in

changing data on the data bus.

Timeout Mode

The timeout mode uses the received data stream to control the

counter. The time-out mode forces the C/T into the timer mode.

Each time a received character is transferred from the shift register

to the RxFIFO, the counter is restarted. If a new character is not

received before the counter reaches zero count, the counter ready

bit is set, and an interrupt can be generated. This mode can be used

to indicate when data has been left in the Rx FIFO for more than the

programmed time limit. If the receiver has been programmed to

interrupt the CPU when the receive FIFO is full, and the message

ends before the FIFO is full, the CPU will not be interrupted for the

remaining characters in the RxFIFO.

By programming the C/T such that it would time out in just over one

character time, the above situation could be avoided. The

processor would be interrupted any time the data stream had

stopped for more than one character time. NOTE: This is very

similar to the watch dog time of MR0. The difference is in the

programmability of the delay time and that the watchdog timer is

restarted by either a receiver load to the RxFIFO or a system read

from it.

This mode is enabled by writing the appropriate command to the

command register. Writing an ‘Ax’ to CRA or CRB will invoke the

timeout mode for that channel. Writing a ‘Cx’ to CRA or CRB will

disable the timeout mode. Only one receiver should use this mode

at a time. However, if both are on, the timeout occurs after both

receivers have been inactive for the timeout period. The start of the

C/T will be on the logical or of the two receivers.

The timeout mode disables the regular START/STOP counter

commands and puts the C/T into counter mode under the control of

the received data stream. Each time a received character is

transferred from the shift register to the RxFIFO, the C/T is stopped

after one C/T clock, reloaded with the value in CTUR and CTLR and

then restarted on the next C/T clock. If the C/T is allowed to end the

count before a new character has been received, the counter ready

bit, ISR[3], will be set. If IMR[3] is set, this will generate an interrupt.

Since receiving a character restarts the C/T, the receipt of a

character after the C/T has timed out will clear the counter ready bit,

ISR[3], and the interrupt. Invoking the ‘Set Timeout Mode On’

command, CRx=‘Ax’, will also clear the counter ready bit and stop

the counter until the next character is received.

The counter timer is controlled with six commands: Start/Stop C/T,

Read/Write Counter/Timer lower register and Read/Write

Counter/Timer upper register. These commands have slight

differences depending on the mode of operation. Please see the

detail of the commands under the CTLR CTUR Register

descriptions.

Time Out Mode Caution

When operating in the special time out mode, it is possible to

generate what appears to be a “false interrupt”, i.e., an interrupt

without a cause. This may result when a time-out interrupt occurs

and then, BEFORE the interrupt is serviced, another character is

received, i.e., the data stream has started again. (The interrupt

latency is longer than the pause in the data strea.) In this case,

when a new character has been receiver, the counter/timer will be

restarted by the receiver, thereby withdrawing its interrupt. If, at this

time, the interrupt service begins for the previously seen interrupt, a

read of the ISR will show the “Counter Ready” bit not set. If nothing

else is interrupting, this read of the ISR will return a x’00 character.

This action may present the appearance of a spurious interrupt.

Receiver and Transmitter

The QUART has four full-duplex asynchronous

receiver/transmitters. The operating frequency for the receiver and

transmitter can be selected independently from the baud rate

generator, the counter/timer, or from an external input.

Registers associated with the communications channel are the

mode registers (MR0, MR1 and MR2) Clock Select Register (CSR),

Command Register (CR), Status Register (SR), Transmit FIFO

(TxFIFO), and the Receive FIFO (RxFIFO). The transmit and

receive FIFOs are each eight characters deep. The receive FIFO

also stores three status bits with each character.

Transmitter

The transmitter accepts parallel data from the CPU and converts it

to a serial bit stream on the TxD output pin. It automatically sends a

start bit followed by the programmed number of data bits, an

optional parity bit, and the programmed number of stop bits. The

least significant bit is sent first. Following the transmission of the

stop bits, if a new character is not available in the TxFIFO, the TxD

output remains high and the TxEMT bit in the SR will be set to 1.

Transmission resumes and the TxEMT bit is cleared when the CPU

loads a new character in the TxFIFO. In the 16X clock mode, this

also re-synchronizes the internal 1X transmitter clock so that

transmission of the new character begins with minimum delay.

If the transmitter is disabled it continues operating until the character

currently being transmitted and any characters in the TxFIFO,

including parity and stop bits, have been transmitted. New data

cannot be loaded to the TxFIFO when the transmitter is disabled.

The transmitter can be forced to send a break (a continuous low

condition) by issuing a START BREAK command via the CR

transmitter reset..

TxFIFO

The TxFIFO empty positions are encoded as a three bit number for

presentation to the bidding logic. The coding will equal the number

of bytes that remain to be filled. That is, a binary number of 101 will

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