SC28C94 datasheet(34/38 Pages) PHILIPS

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Philips Semiconductors

Product specification

SC28C94

Quad universal asynchronous receiver/transmitter (QUART)

1998 Aug 19

through the most significant 6 bits. The result of this is that the

channel value does not ’bid’. However the logic is such that other

parts of the bid being equal the condition of the highest channel will

be captured in CIR. The increasing order of the channels is A, B, C,

D. Thus channel D is the ”strongest” of the four.

It could be that the giving the highest strength to channel D may,

from time to time, not be what would be most desired. Further it

may be desired to alter the authority of a channel’s bid. This may

be done by setting the Rx and/or Tx interrupt bits in MR0 and MR1

to values different than zero. This will have the effect of not allowing

the associated receiver or transmitter to bid until its FIFO reaches a

particular fill level. Although this compromises the idea of the

bidding interrupt scheme, it is entirely safe to use. In fact it is setting

of MR0 and MR1 interrupt bits to zero that causes the receiver to

stop bidding when it is empty and causes the transmitter to stop

bidding when it is full. Altering the MR0 and MR1 interrupt bits only

changes the level at which the Rx & Tx bidding is stopped.

See the “Interrupt Note on 28C94” which refers to the use of the MR

registers in controlling the Rx and Tx bidding.

In normal operation the character of an interrupt will be controlled by

the above registers in conjunction with the IMR (Interrupt Mask

enable bidding of any particular source. Recall that the QUART has

18 functions which may generate an interrupt.

The format of the interrupt vector is controlled by the ICR[1:0] bits.

The formats are shown in Table 10. The purpose of the vector

modification is to allow the interrupting source (either channel or

type and channel) to direct the processor to appropriate service

routine. We have found that some users wish to use extremely tight

loops for the service routines and find the addition of several tests of

status bytes to be very ’expensive’ in processor time.

Table 10.

Configuration of Interrupt Vector for the QUART

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

Interrupt vector for

→

ICR[1 0] 00

INTERRUPT VECTOR FORMATS (Controlled by ICR[1:0])

ICR[1:0]=00

IVR[7:0]

Full interrupt vector

Interrupt vector for

→

ICR[1 0] 01

ICR[1:0]=01

IVR[7:2]

ICR[1:0]

Interrupt vector 6 MSBs

Channel number

Interrupt vector for

→

ICR[1 0] 10

ICR[1:0]=10

IVR[7:5]

ICR[4:2]

ICR[1:0]

Interrupt vector 3 MSBs

Interrupt type

Channel number

Interrupt vector for

→

ICR[1 0] 11 (I hibit)

ICR[1:0]=11 (Inhibit)

Inhibit vector output. (Set bus to FFh)

CURRENT INTERRUPT REGISTER FORMAT CIR[7:0]

Rx or Tx byte count

Interrupt type: R/Tx CT COS BRK

Channel number

INTERRUPT CONTROL REGISTER FORMAT ICR[0:7]

Interrupt threshold ICR[7:2]

Interrupt vector format

ICR[1:0]

NOTE ON QUART INTERFACE TO ITS

CONTROLLING PROCESSOR

The QUART, has been designed to interface in either the

synchronous interrupt environment (without DACKN) or the

asynchronous interrupt environment (with DACKN). The 80xxx

devices of Intel design are usually operated in a synchronous

interrupt mode while those of Motorola design, 68xxx devices,

operate in an asynchronous interrupt mode.

Note: Synchronous and asynchronous interrupt modes are not

in any way associated with synchronous or asynchronous data

transmission.

The QUART has been designed with the pins required to service

either interface. In general then it is probable that in any application

some of the interface pins will not be used. This note discusses

what is required for the ”text book” connections of the two methods.

It should be noted that features of either method are not mutually

exclusive.

The interface pins are all active low. (at VSS or ground) The pins

used for normal reading and writing to the QUART (the generation of

a bus cycle) are CEN (Chip Enable), RDN (Read Enable), WRN

(Write Enable). The pins used in the interrupt service are IRQN

(Interrupt Request), IACKN (Interrupt Acknowledge). The pin used

for data transfer is DACKN (Data Acknowledge). IRQN and DACKN

are open drain outputs.

DACKN signaling can be enabled or disabled via writing to address

27h or 26h respectively. Note that if DACKN is enabled that writing

to the QUART will occur on the falling edge of DACKN. The use of

hardware reset (required at power up) enables DACKN.

The Asynchronous Interface

Those familiar with 68xxx I/O will note the use of the two pins RDN

and WRN to be in conflict with 68xxx devices use of the one R/WN

pin. The R/WN must be inverted such that the R/WN may drive the

WRN input while the inversion of R/WN drives the RDN input. It is

good practice to condition the inversion of R/WN such that RDN will

not become active on the termination of a write to the QUART while

CEN is still asserted. These short periods of read could upset FIFO

pointers in the chip.

During a read of the QUART DACKN signals that valid data is on the

data bus. During a write to the QUART DACKN signals that data

placed on the bus by the control processor has been written to the

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